2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "base/misc.hh"
43 #include "cpu/testers/rubytest/Check.hh"
44 #include "cpu/testers/rubytest/RubyTester.hh"
45 #include "debug/RubyTest.hh"
46 #include "mem/ruby/common/Global.hh"
47 #include "mem/ruby/common/SubBlock.hh"
48 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
49 #include "mem/ruby/system/System.hh"
50 #include "sim/sim_exit.hh"
51 #include "sim/system.hh"
53 RubyTester::RubyTester(const Params
*p
)
54 : MemObject(p
), checkStartEvent(this),
55 _masterId(p
->system
->getMasterId(name())),
56 m_num_cpus(p
->num_cpus
),
57 m_checks_to_complete(p
->checks_to_complete
),
58 m_deadlock_threshold(p
->deadlock_threshold
),
59 m_wakeup_frequency(p
->wakeup_frequency
),
60 m_check_flush(p
->check_flush
),
61 m_num_inst_ports(p
->port_cpuInstPort_connection_count
)
63 m_checks_completed
= 0;
66 // Create the requested inst and data ports and place them on the
67 // appropriate read and write port lists. The reason for the subtle
68 // difference between inst and data ports vs. read and write ports is
69 // from the tester's perspective, it only needs to know whether a port
70 // supports reads (checks) or writes (actions). Meanwhile, the protocol
71 // controllers have data ports (support read and writes) or inst ports
72 // (support only reads).
73 // Note: the inst ports are the lowest elements of the readPort vector,
74 // then the data ports are added to the readPort vector
76 for (int i
= 0; i
< p
->port_cpuInstPort_connection_count
; ++i
) {
77 readPorts
.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i
),
79 RubyTester::CpuPort::InstOnly
));
81 for (int i
= 0; i
< p
->port_cpuDataPort_connection_count
; ++i
) {
83 port
= new CpuPort(csprintf("%s-dataPort%d", name(), i
), this, i
,
84 RubyTester::CpuPort::DataOnly
);
85 readPorts
.push_back(port
);
86 writePorts
.push_back(port
);
89 // add the check start event to the event queue
90 schedule(checkStartEvent
, 1);
93 RubyTester::~RubyTester()
95 delete m_checkTable_ptr
;
96 // Only delete the readPorts since the writePorts are just a subset
97 for (int i
= 0; i
< readPorts
.size(); i
++)
104 assert(writePorts
.size() > 0 && readPorts
.size() > 0);
106 m_last_progress_vector
.resize(m_num_cpus
);
107 for (int i
= 0; i
< m_last_progress_vector
.size(); i
++) {
108 m_last_progress_vector
[i
] = 0;
111 m_num_writers
= writePorts
.size();
112 m_num_readers
= readPorts
.size();
114 m_checkTable_ptr
= new CheckTable(m_num_writers
, m_num_readers
, this);
118 RubyTester::getMasterPort(const std::string
&if_name
, int idx
)
120 if (if_name
!= "cpuInstPort" && if_name
!= "cpuDataPort") {
121 // pass it along to our super class
122 return MemObject::getMasterPort(if_name
, idx
);
124 if (if_name
== "cpuInstPort") {
125 printf("print getting inst port %d\n", idx
);
126 if (idx
> m_num_inst_ports
) {
127 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
131 // inst ports directly map to the lowest readPort elements
133 return *readPorts
[idx
];
135 assert(if_name
== "cpuDataPort");
137 // add the inst port offset to translate to the correct read port
140 int read_idx
= idx
+ m_num_inst_ports
;
141 if (read_idx
>= static_cast<int>(readPorts
.size())) {
142 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
145 return *readPorts
[read_idx
];
151 RubyTester::CpuPort::recvAtomic(PacketPtr pkt
)
153 panic("RubyTester::CpuPort::recvAtomic() not implemented!\n");
158 RubyTester::CpuPort::recvTiming(PacketPtr pkt
)
160 // retrieve the subblock and call hitCallback
161 RubyTester::SenderState
* senderState
=
162 safe_cast
<RubyTester::SenderState
*>(pkt
->senderState
);
163 SubBlock
* subblock
= senderState
->subBlock
;
164 assert(subblock
!= NULL
);
166 // pop the sender state from the packet
167 pkt
->senderState
= senderState
->saved
;
169 tester
->hitCallback(idx
, subblock
);
171 // Now that the tester has completed, delete the senderState
172 // (includes sublock) and the packet, then return
180 RubyTester::getReadableCpuPort(int idx
)
182 assert(idx
>= 0 && idx
< readPorts
.size());
184 return readPorts
[idx
];
188 RubyTester::getWritableCpuPort(int idx
)
190 assert(idx
>= 0 && idx
< writePorts
.size());
192 return writePorts
[idx
];
196 RubyTester::hitCallback(NodeID proc
, SubBlock
* data
)
198 // Mark that we made progress
199 m_last_progress_vector
[proc
] = g_eventQueue_ptr
->getTime();
201 DPRINTF(RubyTest
, "completed request for proc: %d\n", proc
);
202 DPRINTF(RubyTest
, "addr: 0x%x, size: %d, data: ",
203 data
->getAddress(), data
->getSize());
204 for (int byte
= 0; byte
< data
->getSize(); byte
++) {
205 DPRINTF(RubyTest
, "%d", data
->getByte(byte
));
207 DPRINTF(RubyTest
, "\n");
209 // This tells us our store has 'completed' or for a load gives us
210 // back the data to make the check
211 Check
* check_ptr
= m_checkTable_ptr
->getCheck(data
->getAddress());
212 assert(check_ptr
!= NULL
);
213 check_ptr
->performCallback(proc
, data
);
219 if (m_checks_completed
< m_checks_to_complete
) {
220 // Try to perform an action or check
221 Check
* check_ptr
= m_checkTable_ptr
->getRandomCheck();
222 assert(check_ptr
!= NULL
);
223 check_ptr
->initiate();
227 schedule(checkStartEvent
, curTick() + m_wakeup_frequency
);
229 exitSimLoop("Ruby Tester completed");
234 RubyTester::checkForDeadlock()
236 int size
= m_last_progress_vector
.size();
237 Time current_time
= g_eventQueue_ptr
->getTime();
238 for (int processor
= 0; processor
< size
; processor
++) {
239 if ((current_time
- m_last_progress_vector
[processor
]) >
240 m_deadlock_threshold
) {
241 panic("Deadlock detected: current_time: %d last_progress_time: %d "
242 "difference: %d processor: %d\n",
243 current_time
, m_last_progress_vector
[processor
],
244 current_time
- m_last_progress_vector
[processor
], processor
);
250 RubyTester::print(std::ostream
& out
) const
252 out
<< "[RubyTester]" << std::endl
;
256 RubyTesterParams::create()
258 return new RubyTester(this);