2 * Copyright (c) 2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43 #define __CPU_RUBYTEST_RUBYTESTER_HH__
49 #include "cpu/testers/rubytest/CheckTable.hh"
50 #include "mem/packet.hh"
51 #include "mem/port.hh"
52 #include "mem/ruby/common/SubBlock.hh"
53 #include "mem/ruby/common/TypeDefines.hh"
54 #include "params/RubyTester.hh"
55 #include "sim/clocked_object.hh"
57 class RubyTester : public ClockedObject
60 class CpuPort : public RequestPort
64 // index for m_last_progress_vector and hitCallback
69 // Currently, each instatiation of the RubyTester::CpuPort supports
70 // only instruction or data requests, not both. However, for those
71 // RubyPorts that support both types of requests, separate InstOnly
72 // and DataOnly CpuPorts will map to that RubyPort
74 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
76 : RequestPort(_name, _tester, _id), tester(_tester),
81 virtual bool recvTimingResp(PacketPtr pkt);
82 virtual void recvReqRetry()
83 { panic("%s does not expect a retry\n", name()); }
86 struct SenderState : public Packet::SenderState
90 SenderState(Addr addr, int size) : subBlock(addr, size) {}
94 typedef RubyTesterParams Params;
95 RubyTester(const Params *p);
98 Port &getPort(const std::string &if_name,
99 PortID idx=InvalidPortID) override;
101 bool isInstOnlyCpuPort(int idx);
102 bool isInstDataCpuPort(int idx);
104 RequestPort* getReadableCpuPort(int idx);
105 RequestPort* getWritableCpuPort(int idx);
107 void init() override;
111 void incrementCheckCompletions() { m_checks_completed++; }
113 void printStats(std::ostream& out) const {}
115 void printConfig(std::ostream& out) const {}
117 void print(std::ostream& out) const;
118 bool getCheckFlush() { return m_check_flush; }
120 RequestorID requestorId() { return _requestorId; }
122 EventFunctionWrapper checkStartEvent;
124 RequestorID _requestorId;
127 void hitCallback(NodeID proc, SubBlock* data);
129 void checkForDeadlock();
131 // Private copy constructor and assignment operator
132 RubyTester(const RubyTester& obj);
133 RubyTester& operator=(const RubyTester& obj);
135 CheckTable* m_checkTable_ptr;
136 std::vector<Cycles> m_last_progress_vector;
139 uint64_t m_checks_completed;
140 std::vector<RequestPort*> writePorts;
141 std::vector<RequestPort*> readPorts;
142 uint64_t m_checks_to_complete;
143 int m_deadlock_threshold;
146 int m_wakeup_frequency;
148 int m_num_inst_only_ports;
149 int m_num_inst_data_ports;
153 operator<<(std::ostream& out, const RubyTester& obj)
160 #endif // __CPU_RUBYTEST_RUBYTESTER_HH__