mem: Add const getters for write packet data
[gem5.git] / src / cpu / testers / rubytest / RubyTester.py
1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
3 # All rights reserved.
4 #
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
15 #
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #
28
29 from MemObject import MemObject
30 from m5.params import *
31 from m5.proxy import *
32
33 class RubyTester(MemObject):
34 type = 'RubyTester'
35 cxx_header = "cpu/testers/rubytest/RubyTester.hh"
36 num_cpus = Param.Int("number of cpus / RubyPorts")
37 cpuDataPort = VectorMasterPort("the cpu data cache ports")
38 cpuInstPort = VectorMasterPort("the cpu inst cache ports")
39 checks_to_complete = Param.Int(100, "checks to complete")
40 deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
41 wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
42 check_flush = Param.Bool(False, "check cache flushing")
43 system = Param.System(Parent.any, "System we belong to")