src/cpu/testers/traffic_gen/TrafficGen.py

   1 # Copyright (c) 2012 ARM Limited
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  35 #
  36 # Authors: Thomas Grass
  37 #          Andreas Hansson
  38 #          Sascha Bischoff
  39
  40 from m5.params import *
  41 from m5.proxy import *
  42 from MemObject import MemObject
  43
  44 # The traffic generator is a master module that generates stimuli for
  45 # the memory system, based on a collection of simple behaviours that
  46 # are either probabilistic or based on traces. It can be used stand
  47 # alone for creating test cases for interconnect and memory
  48 # controllers, or function as a black-box replacement for system
  49 # components that are not yet modelled in detail, e.g. a video engine
  50 # or baseband subsystem in an SoC.
  51 #
  52 # The traffic generator has a single master port that is used to send
  53 # requests, independent of the specific behaviour. The behaviour of
  54 # the traffic generator is specified in a configuration file, and this
  55 # file describes a state transition graph where each state is a
  56 # specific generator behaviour. Examples include idling, generating
  57 # linear address sequences, random sequences and replay of captured
  58 # traces. By describing these behaviours as states, it is straight
  59 # forward to create very complex behaviours, simply by arranging them
  60 # in graphs. The graph transitions can also be annotated with
  61 # probabilities, effectively making it a Markov Chain.
  62 class TrafficGen(MemObject):
  63     type = 'TrafficGen'
  64     cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
  65
  66     # Port used for sending requests and receiving responses
  67     port = MasterPort("Master port")
  68
  69     # Config file to parse for the state descriptions
  70     config_file = Param.String("Configuration file describing the behaviour")
  71
  72     # System used to determine the mode of the memory system
  73     system = Param.System(Parent.any, "System this generator is part of")