src/cpu/testers/traffic_gen/base.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2016-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
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  17  * notice, this list of conditions and the following disclaimer;
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  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Thomas Grass
  38  *          Andreas Hansson
  39  *          Sascha Bischoff
  40  */
  41
  42 #ifndef __CPU_TRAFFIC_GEN_BASE_HH__
  43 #define __CPU_TRAFFIC_GEN_BASE_HH__
  44
  45 #include <memory>
  46 #include <tuple>
  47
  48 #include "base/statistics.hh"
  49 #include "mem/mem_object.hh"
  50 #include "mem/qport.hh"
  51
  52 class BaseGen;
  53 class StreamGen;
  54 class System;
  55 struct BaseTrafficGenParams;
  56
  57 /**
  58  * The traffic generator is a master module that generates stimuli for
  59  * the memory system, based on a collection of simple generator
  60  * behaviours that are either probabilistic or based on traces. It can
  61  * be used stand alone for creating test cases for interconnect and
  62  * memory controllers, or function as a black box replacement for
  63  * system components that are not yet modelled in detail, e.g. a video
  64  * engine or baseband subsystem.
  65  */
  66 class BaseTrafficGen : public MemObject
  67 {
  68     friend class BaseGen;
  69
  70   protected: // Params
  71     /**
  72      * The system used to determine which mode we are currently operating
  73      * in.
  74      */
  75     System *const system;
  76
  77     /**
  78      * Determine whether to add elasticity in the request injection,
  79      * thus responding to backpressure by slowing things down.
  80      */
  81     const bool elasticReq;
  82
  83     /**
  84      * Time to tolerate waiting for retries (not making progress),
  85      * until we declare things broken.
  86      */
  87     const Tick progressCheck;
  88
  89   private:
  90     /**
  91      * Receive a retry from the neighbouring port and attempt to
  92      * resend the waiting packet.
  93      */
  94     void recvReqRetry();
  95
  96     /** Transition to the next generator */
  97     void transition();
  98
  99     /**
 100      * Schedule the update event based on nextPacketTick and
 101      * nextTransitionTick.
 102      */
 103     void scheduleUpdate();
 104
 105     /**
 106      * Method to inform the user we have made no progress.
 107      */
 108     void noProgress();
 109
 110     /**
 111      * Event to keep track of our progress, or lack thereof.
 112      */
 113     EventFunctionWrapper noProgressEvent;
 114
 115     /** Time of next transition */
 116     Tick nextTransitionTick;
 117
 118     /** Time of the next packet. */
 119     Tick nextPacketTick;
 120
 121
 122     /** Master port specialisation for the traffic generator */
 123     class TrafficGenPort : public MasterPort
 124     {
 125       public:
 126
 127         TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
 128             : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
 129         { }
 130
 131       protected:
 132
 133         void recvReqRetry() { trafficGen.recvReqRetry(); }
 134
 135         bool recvTimingResp(PacketPtr pkt);
 136
 137         void recvTimingSnoopReq(PacketPtr pkt) { }
 138
 139         void recvFunctionalSnoop(PacketPtr pkt) { }
 140
 141         Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
 142
 143       private:
 144
 145         BaseTrafficGen& trafficGen;
 146
 147     };
 148
 149     /**
 150      * Schedules event for next update and generates a new packet or
 151      * requests a new generatoir depending on the current time.
 152      */
 153     void update();
 154
 155     /** The instance of master port used by the traffic generator. */
 156     TrafficGenPort port;
 157
 158     /** Packet waiting to be sent. */
 159     PacketPtr retryPkt;
 160
 161     /** Tick when the stalled packet was meant to be sent. */
 162     Tick retryPktTick;
 163
 164     /** Event for scheduling updates */
 165     EventFunctionWrapper updateEvent;
 166
 167     /** Count the number of dropped requests. */
 168     Stats::Scalar numSuppressed;
 169
 170   private: // Stats
 171     /** Count the number of generated packets. */
 172     Stats::Scalar numPackets;
 173
 174     /** Count the number of retries. */
 175     Stats::Scalar numRetries;
 176
 177     /** Count the time incurred from back-pressure. */
 178     Stats::Scalar retryTicks;
 179
 180   public:
 181     BaseTrafficGen(const BaseTrafficGenParams* p);
 182
 183     ~BaseTrafficGen();
 184
 185     Port &getPort(const std::string &if_name,
 186                   PortID idx=InvalidPortID) override;
 187
 188     void init() override;
 189
 190     DrainState drain() override;
 191
 192     void serialize(CheckpointOut &cp) const override;
 193     void unserialize(CheckpointIn &cp) override;
 194
 195     /** Register statistics */
 196     void regStats() override;
 197
 198   public: // Generator factory methods
 199     std::shared_ptr<BaseGen> createIdle(Tick duration);
 200     std::shared_ptr<BaseGen> createExit(Tick duration);
 201
 202     std::shared_ptr<BaseGen> createLinear(
 203         Tick duration,
 204         Addr start_addr, Addr end_addr, Addr blocksize,
 205         Tick min_period, Tick max_period,
 206         uint8_t read_percent, Addr data_limit);
 207
 208     std::shared_ptr<BaseGen> createRandom(
 209         Tick duration,
 210         Addr start_addr, Addr end_addr, Addr blocksize,
 211         Tick min_period, Tick max_period,
 212         uint8_t read_percent, Addr data_limit);
 213
 214     std::shared_ptr<BaseGen> createDram(
 215         Tick duration,
 216         Addr start_addr, Addr end_addr, Addr blocksize,
 217         Tick min_period, Tick max_period,
 218         uint8_t read_percent, Addr data_limit,
 219         unsigned int num_seq_pkts, unsigned int page_size,
 220         unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
 221         unsigned int addr_mapping,
 222         unsigned int nbr_of_ranks);
 223
 224     std::shared_ptr<BaseGen> createDramRot(
 225         Tick duration,
 226         Addr start_addr, Addr end_addr, Addr blocksize,
 227         Tick min_period, Tick max_period,
 228         uint8_t read_percent, Addr data_limit,
 229         unsigned int num_seq_pkts, unsigned int page_size,
 230         unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
 231         unsigned int addr_mapping,
 232         unsigned int nbr_of_ranks,
 233         unsigned int max_seq_count_per_rank);
 234
 235     std::shared_ptr<BaseGen> createTrace(
 236         Tick duration,
 237         const std::string& trace_file, Addr addr_offset);
 238
 239   protected:
 240     void start();
 241
 242     virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
 243
 244     /**
 245      * MasterID used in generated requests.
 246      */
 247     const MasterID masterID;
 248
 249     /** Currently active generator */
 250     std::shared_ptr<BaseGen> activeGenerator;
 251
 252     /** Stream/SubStreamID Generator */
 253     std::unique_ptr<StreamGen> streamGenerator;
 254 };
 255
 256 #endif //__CPU_TRAFFIC_GEN_BASE_HH__