6f419e88d80497abc2fbf99e7e4d96a3c26d2f29
[gem5.git] / src / cpu / testers / traffic_gen / base.hh
1 /*
2 * Copyright (c) 2012-2013, 2016-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef __CPU_TRAFFIC_GEN_BASE_HH__
39 #define __CPU_TRAFFIC_GEN_BASE_HH__
40
41 #include <memory>
42 #include <tuple>
43 #include <unordered_map>
44
45 #include "base/statistics.hh"
46 #include "enums/AddrMap.hh"
47 #include "mem/qport.hh"
48 #include "sim/clocked_object.hh"
49
50 class BaseGen;
51 class StreamGen;
52 class System;
53 struct BaseTrafficGenParams;
54
55 /**
56 * The traffic generator is a master module that generates stimuli for
57 * the memory system, based on a collection of simple generator
58 * behaviours that are either probabilistic or based on traces. It can
59 * be used stand alone for creating test cases for interconnect and
60 * memory controllers, or function as a black box replacement for
61 * system components that are not yet modelled in detail, e.g. a video
62 * engine or baseband subsystem.
63 */
64 class BaseTrafficGen : public ClockedObject
65 {
66 friend class BaseGen;
67
68 protected: // Params
69 /**
70 * The system used to determine which mode we are currently operating
71 * in.
72 */
73 System *const system;
74
75 /**
76 * Determine whether to add elasticity in the request injection,
77 * thus responding to backpressure by slowing things down.
78 */
79 const bool elasticReq;
80
81 /**
82 * Time to tolerate waiting for retries (not making progress),
83 * until we declare things broken.
84 */
85 const Tick progressCheck;
86
87 private:
88 /**
89 * Receive a retry from the neighbouring port and attempt to
90 * resend the waiting packet.
91 */
92 void recvReqRetry();
93
94 void retryReq();
95
96 bool recvTimingResp(PacketPtr pkt);
97
98 /** Transition to the next generator */
99 void transition();
100
101 /**
102 * Schedule the update event based on nextPacketTick and
103 * nextTransitionTick.
104 */
105 void scheduleUpdate();
106
107 /**
108 * Method to inform the user we have made no progress.
109 */
110 void noProgress();
111
112 /**
113 * Event to keep track of our progress, or lack thereof.
114 */
115 EventFunctionWrapper noProgressEvent;
116
117 /** Time of next transition */
118 Tick nextTransitionTick;
119
120 /** Time of the next packet. */
121 Tick nextPacketTick;
122
123 const int maxOutstandingReqs;
124
125
126 /** Master port specialisation for the traffic generator */
127 class TrafficGenPort : public RequestPort
128 {
129 public:
130
131 TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
132 : RequestPort(name, &traffic_gen), trafficGen(traffic_gen)
133 { }
134
135 protected:
136
137 void recvReqRetry() { trafficGen.recvReqRetry(); }
138
139 bool recvTimingResp(PacketPtr pkt)
140 { return trafficGen.recvTimingResp(pkt); }
141
142 void recvTimingSnoopReq(PacketPtr pkt) { }
143
144 void recvFunctionalSnoop(PacketPtr pkt) { }
145
146 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
147
148 private:
149
150 BaseTrafficGen& trafficGen;
151
152 };
153
154 /**
155 * Schedules event for next update and generates a new packet or
156 * requests a new generatoir depending on the current time.
157 */
158 void update();
159
160 /** The instance of master port used by the traffic generator. */
161 TrafficGenPort port;
162
163 /** Packet waiting to be sent. */
164 PacketPtr retryPkt;
165
166 /** Tick when the stalled packet was meant to be sent. */
167 Tick retryPktTick;
168
169 /** Set when we blocked waiting for outstanding reqs */
170 bool blockedWaitingResp;
171
172 /**
173 * Puts this packet in the waitingResp list and returns true if
174 * we are above the maximum number of oustanding requests.
175 */
176 bool allocateWaitingRespSlot(PacketPtr pkt)
177 {
178 assert(waitingResp.find(pkt->req) == waitingResp.end());
179 assert(pkt->needsResponse());
180
181 waitingResp[pkt->req] = curTick();
182
183 return (maxOutstandingReqs > 0) &&
184 (waitingResp.size() > maxOutstandingReqs);
185 }
186
187 /** Event for scheduling updates */
188 EventFunctionWrapper updateEvent;
189
190 protected: // Stats
191 /** Reqs waiting for response **/
192 std::unordered_map<RequestPtr,Tick> waitingResp;
193
194 struct StatGroup : public Stats::Group {
195 StatGroup(Stats::Group *parent);
196
197 /** Count the number of dropped requests. */
198 Stats::Scalar numSuppressed;
199
200 /** Count the number of generated packets. */
201 Stats::Scalar numPackets;
202
203 /** Count the number of retries. */
204 Stats::Scalar numRetries;
205
206 /** Count the time incurred from back-pressure. */
207 Stats::Scalar retryTicks;
208
209 /** Count the number of bytes read. */
210 Stats::Scalar bytesRead;
211
212 /** Count the number of bytes written. */
213 Stats::Scalar bytesWritten;
214
215 /** Total num of ticks read reqs took to complete */
216 Stats::Scalar totalReadLatency;
217
218 /** Total num of ticks write reqs took to complete */
219 Stats::Scalar totalWriteLatency;
220
221 /** Count the number reads. */
222 Stats::Scalar totalReads;
223
224 /** Count the number writes. */
225 Stats::Scalar totalWrites;
226
227 /** Avg num of ticks each read req took to complete */
228 Stats::Formula avgReadLatency;
229
230 /** Avg num of ticks each write reqs took to complete */
231 Stats::Formula avgWriteLatency;
232
233 /** Read bandwidth in bytes/s */
234 Stats::Formula readBW;
235
236 /** Write bandwidth in bytes/s */
237 Stats::Formula writeBW;
238 } stats;
239
240 public:
241 BaseTrafficGen(const BaseTrafficGenParams* p);
242
243 ~BaseTrafficGen();
244
245 Port &getPort(const std::string &if_name,
246 PortID idx=InvalidPortID) override;
247
248 void init() override;
249
250 DrainState drain() override;
251
252 void serialize(CheckpointOut &cp) const override;
253 void unserialize(CheckpointIn &cp) override;
254
255 public: // Generator factory methods
256 std::shared_ptr<BaseGen> createIdle(Tick duration);
257 std::shared_ptr<BaseGen> createExit(Tick duration);
258
259 std::shared_ptr<BaseGen> createLinear(
260 Tick duration,
261 Addr start_addr, Addr end_addr, Addr blocksize,
262 Tick min_period, Tick max_period,
263 uint8_t read_percent, Addr data_limit);
264
265 std::shared_ptr<BaseGen> createRandom(
266 Tick duration,
267 Addr start_addr, Addr end_addr, Addr blocksize,
268 Tick min_period, Tick max_period,
269 uint8_t read_percent, Addr data_limit);
270
271 std::shared_ptr<BaseGen> createDram(
272 Tick duration,
273 Addr start_addr, Addr end_addr, Addr blocksize,
274 Tick min_period, Tick max_period,
275 uint8_t read_percent, Addr data_limit,
276 unsigned int num_seq_pkts, unsigned int page_size,
277 unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
278 Enums::AddrMap addr_mapping,
279 unsigned int nbr_of_ranks);
280
281 std::shared_ptr<BaseGen> createDramRot(
282 Tick duration,
283 Addr start_addr, Addr end_addr, Addr blocksize,
284 Tick min_period, Tick max_period,
285 uint8_t read_percent, Addr data_limit,
286 unsigned int num_seq_pkts, unsigned int page_size,
287 unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
288 Enums::AddrMap addr_mapping,
289 unsigned int nbr_of_ranks,
290 unsigned int max_seq_count_per_rank);
291
292 std::shared_ptr<BaseGen> createHybrid(
293 Tick duration,
294 Addr start_addr_dram, Addr end_addr_dram, Addr blocksize_dram,
295 Addr start_addr_nvm, Addr end_addr_nvm, Addr blocksize_nvm,
296 Tick min_period, Tick max_period,
297 uint8_t read_percent, Addr data_limit,
298 unsigned int num_seq_pkts_dram, unsigned int page_size_dram,
299 unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram,
300 unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
301 unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm,
302 Enums::AddrMap addr_mapping,
303 unsigned int nbr_of_ranks_dram,
304 unsigned int nbr_of_ranks_nvm,
305 uint8_t nvm_percent);
306
307 std::shared_ptr<BaseGen> createNvm(
308 Tick duration,
309 Addr start_addr, Addr end_addr, Addr blocksize,
310 Tick min_period, Tick max_period,
311 uint8_t read_percent, Addr data_limit,
312 unsigned int num_seq_pkts, unsigned int buffer_size,
313 unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
314 Enums::AddrMap addr_mapping,
315 unsigned int nbr_of_ranks);
316
317 std::shared_ptr<BaseGen> createTrace(
318 Tick duration,
319 const std::string& trace_file, Addr addr_offset);
320
321 protected:
322 void start();
323
324 virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
325
326 /**
327 * MasterID used in generated requests.
328 */
329 const MasterID masterID;
330
331 /** Currently active generator */
332 std::shared_ptr<BaseGen> activeGenerator;
333
334 /** Stream/SubStreamID Generator */
335 std::unique_ptr<StreamGen> streamGenerator;
336 };
337
338 #endif //__CPU_TRAFFIC_GEN_BASE_HH__