src/cpu/testers/traffic_gen/dram_gen.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2016-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed here under.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "cpu/testers/traffic_gen/dram_gen.hh"
  39
  40 #include <algorithm>
  41
  42 #include "base/random.hh"
  43 #include "base/trace.hh"
  44 #include "debug/TrafficGen.hh"
  45 #include "enums/AddrMap.hh"
  46
  47 DramGen::DramGen(SimObject &obj,
  48                  RequestorID requestor_id, Tick _duration,
  49                  Addr start_addr, Addr end_addr,
  50                  Addr _blocksize, Addr cacheline_size,
  51                  Tick min_period, Tick max_period,
  52                  uint8_t read_percent, Addr data_limit,
  53                  unsigned int num_seq_pkts, unsigned int page_size,
  54                  unsigned int nbr_of_banks_DRAM,
  55                  unsigned int nbr_of_banks_util,
  56                  Enums::AddrMap addr_mapping,
  57                  unsigned int nbr_of_ranks)
  58         : RandomGen(obj, requestor_id, _duration, start_addr, end_addr,
  59           _blocksize, cacheline_size, min_period, max_period,
  60           read_percent, data_limit),
  61           numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
  62           isRead(true), pageSize(page_size),
  63           pageBits(floorLog2(page_size / _blocksize)),
  64           bankBits(floorLog2(nbr_of_banks_DRAM)),
  65           blockBits(floorLog2(_blocksize)),
  66           nbrOfBanksDRAM(nbr_of_banks_DRAM),
  67           nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
  68           rankBits(floorLog2(nbr_of_ranks)),
  69           nbrOfRanks(nbr_of_ranks)
  70 {
  71     if (nbr_of_banks_util > nbr_of_banks_DRAM)
  72         fatal("Attempting to use more banks (%d) than "
  73               "what is available (%d)\n",
  74               nbr_of_banks_util, nbr_of_banks_DRAM);
  75 }
  76
  77 PacketPtr
  78 DramGen::getNextPacket()
  79 {
  80     // if this is the first of the packets in series to be generated,
  81     // start counting again
  82     if (countNumSeqPkts == 0) {
  83         countNumSeqPkts = numSeqPkts;
  84
  85         // choose if we generate a read or a write here
  86         isRead = readPercent != 0 &&
  87             (readPercent == 100 || random_mt.random(0, 100) < readPercent);
  88
  89         assert((readPercent == 0 && !isRead) ||
  90                (readPercent == 100 && isRead) ||
  91                readPercent != 100);
  92
  93         // pick a random bank
  94         unsigned int new_bank =
  95             random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
  96
  97         // pick a random rank
  98         unsigned int new_rank =
  99             random_mt.random<unsigned int>(0, nbrOfRanks - 1);
 100
 101         // Generate the start address of the command series
 102         // routine will update addr variable with bank, rank, and col
 103         // bits updated for random traffic mode
 104         genStartAddr(new_bank, new_rank);
 105
 106     } else {
 107         // increment the column by one
 108         if (addrMapping == Enums::RoRaBaCoCh ||
 109             addrMapping == Enums::RoRaBaChCo)
 110             // Simply increment addr by blocksize to increment
 111             // the column by one
 112             addr += blocksize;
 113
 114         else if (addrMapping == Enums::RoCoRaBaCh) {
 115             // Explicity increment the column bits
 116             unsigned int new_col = ((addr / blocksize /
 117                                        nbrOfBanksDRAM / nbrOfRanks) %
 118                                    (pageSize / blocksize)) + 1;
 119             replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
 120                         blockBits + bankBits + rankBits, new_col);
 121         }
 122     }
 123
 124     DPRINTF(TrafficGen, "DramGen::getNextPacket: %c to addr %x, "
 125             "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
 126             isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
 127
 128     // create a new request packet
 129     PacketPtr pkt = getPacket(addr, blocksize,
 130                               isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
 131
 132     // add the amount of data manipulated to the total
 133     dataManipulated += blocksize;
 134
 135     // subtract the number of packets remained to be generated
 136     --countNumSeqPkts;
 137
 138     // return the generated packet
 139     return pkt;
 140 }
 141
 142 void
 143 DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
 144 {
 145     // start by picking a random address in the range
 146     addr = random_mt.random<Addr>(startAddr, endAddr - 1);
 147
 148     // round down to start address of a block, i.e. a DRAM burst
 149     addr -= addr % blocksize;
 150
 151     // insert the bank bits at the right spot, and align the
 152     // address to achieve the required hit length, this involves
 153     // finding the appropriate start address such that all
 154     // sequential packets target successive columns in the same
 155     // page
 156
 157     // for example, if we have a stride size of 192B, which means
 158     // for LPDDR3 where burstsize = 32B we have numSeqPkts = 6,
 159     // the address generated previously can be such that these
 160     // 192B cross the page boundary, hence it needs to be aligned
 161     // so that they all belong to the same page for page hit
 162     unsigned int columns_per_page = pageSize / blocksize;
 163
 164     // pick a random column, but ensure that there is room for
 165     // numSeqPkts sequential columns in the same page
 166     unsigned int new_col =
 167         random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
 168
 169     if (addrMapping == Enums::RoRaBaCoCh ||
 170         addrMapping == Enums::RoRaBaChCo) {
 171         // Block bits, then page bits, then bank bits, then rank bits
 172         replaceBits(addr, blockBits + pageBits + bankBits - 1,
 173                     blockBits + pageBits, new_bank);
 174         replaceBits(addr, blockBits + pageBits - 1, blockBits, new_col);
 175         if (rankBits != 0) {
 176             replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
 177                         blockBits + pageBits + bankBits, new_rank);
 178         }
 179     } else if (addrMapping == Enums::RoCoRaBaCh) {
 180         // Block bits, then bank bits, then rank bits, then page bits
 181         replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
 182         replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
 183                     blockBits + bankBits + rankBits, new_col);
 184         if (rankBits != 0) {
 185             replaceBits(addr, blockBits + bankBits + rankBits - 1,
 186                         blockBits + bankBits, new_rank);
 187         }
 188     }
 189 }