src/cpu/testers/traffic_gen/dram_gen.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
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  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
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  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Thomas Grass
  38  *          Andreas Hansson
  39  *          Sascha Bischoff
  40  *          Neha Agarwal
  41  */
  42
  43 /**
  44  * @file
  45  * Declaration of the DRAM generator for issuing variable page
  46  * hit length requests and bank utilisation.
  47  */
  48
  49 #ifndef __CPU_TRAFFIC_GEN_DRAM_GEN_HH__
  50 #define __CPU_TRAFFIC_GEN_DRAM_GEN_HH__
  51
  52 #include "base/bitfield.hh"
  53 #include "base/intmath.hh"
  54 #include "enums/AddrMap.hh"
  55 #include "mem/packet.hh"
  56 #include "random_gen.hh"
  57
  58 /**
  59  * DRAM specific generator is for issuing request with variable page
  60  * hit length and bank utilization. Currently assumes a single
  61  * channel configuration.
  62  */
  63 class DramGen : public RandomGen
  64 {
  65
  66   public:
  67
  68     /**
  69      * Create a DRAM address sequence generator.
  70      *
  71      * @param obj SimObject owning this sequence generator
  72      * @param master_id MasterID related to the memory requests
  73      * @param _duration duration of this state before transitioning
  74      * @param start_addr Start address
  75      * @param end_addr End address
  76      * @param _blocksize Size used for transactions injected
  77      * @param cacheline_size cache line size in the system
  78      * @param min_period Lower limit of random inter-transaction time
  79      * @param max_period Upper limit of random inter-transaction time
  80      * @param read_percent Percent of transactions that are reads
  81      * @param data_limit Upper limit on how much data to read/write
  82      * @param num_seq_pkts Number of packets per stride, each of _blocksize
  83      * @param page_size Page size (bytes) used in the DRAM
  84      * @param nbr_of_banks_DRAM Total number of banks in DRAM
  85      * @param nbr_of_banks_util Number of banks to utilized,
  86      *                          for N banks, we will use banks: 0->(N-1)
  87      * @param addr_mapping Address mapping to be used,
  88      *                     assumes single channel system
  89      */
  90     DramGen(SimObject &obj,
  91             MasterID master_id, Tick _duration,
  92             Addr start_addr, Addr end_addr,
  93             Addr _blocksize, Addr cacheline_size,
  94             Tick min_period, Tick max_period,
  95             uint8_t read_percent, Addr data_limit,
  96             unsigned int num_seq_pkts, unsigned int page_size,
  97             unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
  98             Enums::AddrMap addr_mapping,
  99             unsigned int nbr_of_ranks);
 100
 101     PacketPtr getNextPacket();
 102
 103     /** Insert bank, rank, and column bits into packed
 104      *  address to create address for 1st command in a
 105      *  series
 106      * @param new_bank Bank number of next packet series
 107      * @param new_rank Rank value of next packet series
 108     */
 109     void genStartAddr(unsigned int new_bank , unsigned int new_rank);
 110
 111   protected:
 112
 113     /** Number of sequential DRAM packets to be generated per cpu request */
 114     const unsigned int numSeqPkts;
 115
 116     /** Track number of sequential packets generated for a request  */
 117     unsigned int countNumSeqPkts;
 118
 119     /** Address of request */
 120     Addr addr;
 121
 122     /** Remember type of requests to be generated in series */
 123     bool isRead;
 124
 125     /** Page size of DRAM */
 126     const unsigned int pageSize;
 127
 128     /** Number of page bits in DRAM address */
 129     const unsigned int pageBits;
 130
 131     /** Number of bank bits in DRAM address*/
 132     const unsigned int bankBits;
 133
 134     /** Number of block bits in DRAM address */
 135     const unsigned int blockBits;
 136
 137     /** Number of banks in DRAM */
 138     const unsigned int nbrOfBanksDRAM;
 139
 140     /** Number of banks to be utilized for a given configuration */
 141     const unsigned int nbrOfBanksUtil;
 142
 143     /** Address mapping to be used */
 144     Enums::AddrMap addrMapping;
 145
 146     /** Number of rank bits in DRAM address*/
 147     const unsigned int rankBits;
 148
 149     /** Number of ranks to be utilized for a given configuration */
 150     const unsigned int nbrOfRanks;
 151
 152 };
 153
 154 #endif