src/cpu/testers/traffic_gen/dram_rot_gen.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2017-2019 ARM Limited
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  37
  38 /**
  39  * @file
  40  * Declaration of DRAM rotation generator that rotates
  41  * through each rank.
  42  */
  43
  44 #ifndef __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__
  45 #define __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__
  46
  47 #include "base/bitfield.hh"
  48 #include "base/intmath.hh"
  49 #include "dram_gen.hh"
  50 #include "enums/AddrMap.hh"
  51 #include "mem/packet.hh"
  52
  53 class DramRotGen : public DramGen
  54 {
  55
  56   public:
  57
  58     /**
  59      * Create a DRAM address sequence generator.
  60      * This sequence generator will rotate through:
  61      * 1) Banks per rank
  62      * 2) Command type (if applicable)
  63      * 3) Ranks per channel
  64      *
  65      * @param obj SimObject owning this sequence generator
  66      * @param requestor_id RequestorID related to the memory requests
  67      * @param _duration duration of this state before transitioning
  68      * @param start_addr Start address
  69      * @param end_addr End address
  70      * @param _blocksize Size used for transactions injected
  71      * @param cacheline_size cache line size in the system
  72      * @param min_period Lower limit of random inter-transaction time
  73      * @param max_period Upper limit of random inter-transaction time
  74      * @param read_percent Percent of transactions that are reads
  75      * @param data_limit Upper limit on how much data to read/write
  76      * @param num_seq_pkts Number of packets per stride, each of _blocksize
  77      * @param page_size Page size (bytes) used in the DRAM
  78      * @param nbr_of_banks_DRAM Total number of banks in DRAM
  79      * @param nbr_of_banks_util Number of banks to utilized,
  80      *                          for N banks, we will use banks: 0->(N-1)
  81      * @param nbr_of_ranks Number of ranks utilized,
  82      * @param addr_mapping Address mapping to be used,
  83      *                     assumes single channel system
  84      */
  85     DramRotGen(SimObject &obj, RequestorID requestor_id, Tick _duration,
  86             Addr start_addr, Addr end_addr,
  87             Addr _blocksize, Addr cacheline_size,
  88             Tick min_period, Tick max_period,
  89             uint8_t read_percent, Addr data_limit,
  90             unsigned int num_seq_pkts, unsigned int page_size,
  91             unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
  92             Enums::AddrMap addr_mapping,
  93             unsigned int nbr_of_ranks,
  94             unsigned int max_seq_count_per_rank)
  95         : DramGen(obj, requestor_id, _duration, start_addr, end_addr,
  96           _blocksize, cacheline_size, min_period, max_period,
  97           read_percent, data_limit,
  98           num_seq_pkts, page_size, nbr_of_banks_DRAM,
  99           nbr_of_banks_util, addr_mapping,
 100           nbr_of_ranks),
 101           maxSeqCountPerRank(max_seq_count_per_rank),
 102           nextSeqCount(0)
 103     {
 104         // Rotating traffic generation can only support a read
 105         // percentage of 0, 50, or 100
 106         if (readPercent != 50  && readPercent != 100 && readPercent != 0) {
 107            fatal("%s: Unsupported read percentage for DramRotGen: %d",
 108                  _name, readPercent);
 109         }
 110     }
 111
 112     PacketPtr getNextPacket();
 113
 114   private:
 115     /** Number of command series issued before the rank is
 116         changed.  Should rotate to the next rank after rorating
 117         throughall the banks for each specified command type     */
 118     const unsigned int maxSeqCountPerRank;
 119
 120     /** Next packet series count used to set rank and bank,
 121         and update isRead Incremented at the start of a new
 122         packet series       */
 123     unsigned int nextSeqCount;
 124 };
 125
 126 #endif