src/cpu/testers/traffic_gen/nvm_gen.hh

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed here under.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Wendy Elsasser
  38  */
  39
  40 /**
  41  * @file
  42  * Declaration of the NVM generator for issuing variable buffer
  43  * hit length requests and bank utilisation.
  44  */
  45
  46 #ifndef __CPU_TRAFFIC_GEN_NVM_GEN_HH__
  47 #define __CPU_TRAFFIC_GEN_NVM_GEN_HH__
  48
  49 #include "base/bitfield.hh"
  50 #include "base/intmath.hh"
  51 #include "enums/AddrMap.hh"
  52 #include "mem/packet.hh"
  53 #include "random_gen.hh"
  54
  55 /**
  56  * NVM specific generator is for issuing request with variable buffer
  57  * hit length and bank utilization. Currently assumes a single
  58  * channel configuration.
  59  */
  60 class NvmGen : public RandomGen
  61 {
  62
  63   public:
  64
  65     /**
  66      * Create a NVM address sequence generator.
  67      *
  68      * @param obj SimObject owning this sequence generator
  69      * @param requestor_id RequestorID related to the memory requests
  70      * @param _duration duration of this state before transitioning
  71      * @param start_addr Start address
  72      * @param end_addr End address
  73      * @param _blocksize Size used for transactions injected
  74      * @param cacheline_size cache line size in the system
  75      * @param min_period Lower limit of random inter-transaction time
  76      * @param max_period Upper limit of random inter-transaction time
  77      * @param read_percent Percent of transactions that are reads
  78      * @param data_limit Upper limit on how much data to read/write
  79      * @param num_seq_pkts Number of packets per stride, each of _blocksize
  80      * @param page_size Buffer size (bytes) used in the NVM
  81      * @param nbr_of_banks Total number of parallel banks in NVM
  82      * @param nbr_of_banks_util Number of banks to utilized,
  83      *                          for N banks, we will use banks: 0->(N-1)
  84      * @param addr_mapping Address mapping to be used,
  85      *                     assumes single channel system
  86      */
  87     NvmGen(SimObject &obj,
  88            RequestorID requestor_id, Tick _duration,
  89            Addr start_addr, Addr end_addr,
  90            Addr _blocksize, Addr cacheline_size,
  91            Tick min_period, Tick max_period,
  92            uint8_t read_percent, Addr data_limit,
  93            unsigned int num_seq_pkts, unsigned int buffer_size,
  94            unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
  95            Enums::AddrMap addr_mapping,
  96            unsigned int nbr_of_ranks);
  97
  98     PacketPtr getNextPacket();
  99
 100     /** Insert bank, rank, and column bits into packed
 101      *  address to create address for 1st command in a
 102      *  series
 103      * @param new_bank Bank number of next packet series
 104      * @param new_rank Rank value of next packet series
 105     */
 106     void genStartAddr(unsigned int new_bank, unsigned int new_rank);
 107
 108   protected:
 109
 110     /** Number of sequential NVM packets to be generated per cpu request */
 111     const unsigned int numSeqPkts;
 112
 113     /** Track number of sequential packets generated for a request  */
 114     unsigned int countNumSeqPkts;
 115
 116     /** Address of request */
 117     Addr addr;
 118
 119     /** Remember type of requests to be generated in series */
 120     bool isRead;
 121
 122     /** Buffer size of NVM */
 123     const unsigned int bufferSize;
 124
 125     /** Number of buffer bits in NVM address */
 126     const unsigned int bufferBits;
 127
 128     /** Number of bank bits in NVM address*/
 129     const unsigned int bankBits;
 130
 131     /** Number of block bits in NVM address */
 132     const unsigned int blockBits;
 133
 134     /** Number of banks in NVM */
 135     const unsigned int nbrOfBanksNVM;
 136
 137     /** Number of banks to be utilized for a given configuration */
 138     const unsigned int nbrOfBanksUtil;
 139
 140     /** Address mapping to be used */
 141     Enums::AddrMap addrMapping;
 142
 143     /** Number of rank bits in NVM address*/
 144     const unsigned int rankBits;
 145
 146     /** Number of ranks to be utilized for a given configuration */
 147     const unsigned int nbrOfRanks;
 148
 149 };
 150
 151 #endif