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44 #include "base/misc.hh"
45 #include "base/trace.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/base.hh"
48 #include "cpu/quiesce_event.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Context.hh"
51 #include "sim/full_system.hh"
54 ThreadContext::compare(ThreadContext
*one
, ThreadContext
*two
)
56 DPRINTF(Context
, "Comparing thread contexts\n");
58 // First loop through the integer registers.
59 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
60 TheISA::IntReg t1
= one
->readIntReg(i
);
61 TheISA::IntReg t2
= two
->readIntReg(i
);
63 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
67 // Then loop through the floating point registers.
68 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
69 TheISA::FloatRegBits t1
= one
->readFloatRegBits(i
);
70 TheISA::FloatRegBits t2
= two
->readFloatRegBits(i
);
72 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
75 for (int i
= 0; i
< TheISA::NumMiscRegs
; ++i
) {
76 TheISA::MiscReg t1
= one
->readMiscRegNoEffect(i
);
77 TheISA::MiscReg t2
= two
->readMiscRegNoEffect(i
);
79 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
83 // loop through the Condition Code registers.
84 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
) {
85 TheISA::CCReg t1
= one
->readCCReg(i
);
86 TheISA::CCReg t2
= two
->readCCReg(i
);
88 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
91 if (!(one
->pcState() == two
->pcState()))
92 panic("PC state doesn't match.");
93 int id1
= one
->cpuId();
94 int id2
= two
->cpuId();
96 panic("CPU ids don't match, one: %d, two: %d", id1
, id2
);
98 id1
= one
->contextId();
99 id2
= two
->contextId();
101 panic("Context ids don't match, one: %d, two: %d", id1
, id2
);
107 serialize(ThreadContext
&tc
, std::ostream
&os
)
109 using namespace TheISA
;
111 FloatRegBits floatRegs
[NumFloatRegs
];
112 for (int i
= 0; i
< NumFloatRegs
; ++i
)
113 floatRegs
[i
] = tc
.readFloatRegBitsFlat(i
);
114 // This is a bit ugly, but needed to maintain backwards
116 arrayParamOut(os
, "floatRegs.i", floatRegs
, NumFloatRegs
);
118 IntReg intRegs
[NumIntRegs
];
119 for (int i
= 0; i
< NumIntRegs
; ++i
)
120 intRegs
[i
] = tc
.readIntRegFlat(i
);
121 SERIALIZE_ARRAY(intRegs
, NumIntRegs
);
123 #ifdef ISA_HAS_CC_REGS
124 CCReg ccRegs
[NumCCRegs
];
125 for (int i
= 0; i
< NumCCRegs
; ++i
)
126 ccRegs
[i
] = tc
.readCCRegFlat(i
);
127 SERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
130 tc
.pcState().serialize(os
);
132 // thread_num and cpu_id are deterministic from the config
136 unserialize(ThreadContext
&tc
, Checkpoint
*cp
, const std::string
§ion
)
138 using namespace TheISA
;
140 FloatRegBits floatRegs
[NumFloatRegs
];
141 // This is a bit ugly, but needed to maintain backwards
143 arrayParamIn(cp
, section
, "floatRegs.i", floatRegs
, NumFloatRegs
);
144 for (int i
= 0; i
< NumFloatRegs
; ++i
)
145 tc
.setFloatRegBitsFlat(i
, floatRegs
[i
]);
147 IntReg intRegs
[NumIntRegs
];
148 UNSERIALIZE_ARRAY(intRegs
, NumIntRegs
);
149 for (int i
= 0; i
< NumIntRegs
; ++i
)
150 tc
.setIntRegFlat(i
, intRegs
[i
]);
152 #ifdef ISA_HAS_CC_REGS
153 CCReg ccRegs
[NumCCRegs
];
154 UNSERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
155 for (int i
= 0; i
< NumCCRegs
; ++i
)
156 tc
.setCCRegFlat(i
, ccRegs
[i
]);
160 pcState
.unserialize(cp
, section
);
163 // thread_num and cpu_id are deterministic from the config
167 takeOverFrom(ThreadContext
&ntc
, ThreadContext
&otc
)
169 assert(ntc
.getProcessPtr() == otc
.getProcessPtr());
171 ntc
.setStatus(otc
.status());
172 ntc
.copyArchRegs(&otc
);
173 ntc
.setContextId(otc
.contextId());
174 ntc
.setThreadId(otc
.threadId());
177 assert(ntc
.getSystemPtr() == otc
.getSystemPtr());
179 BaseCPU
*ncpu(ntc
.getCpuPtr());
181 EndQuiesceEvent
*oqe(otc
.getQuiesceEvent());
183 assert(oqe
->tc
== &otc
);
185 BaseCPU
*ocpu(otc
.getCpuPtr());
187 EndQuiesceEvent
*nqe(ntc
.getQuiesceEvent());
189 assert(nqe
->tc
== &ntc
);
191 if (oqe
->scheduled()) {
192 ncpu
->schedule(nqe
, oqe
->when());
193 ocpu
->deschedule(oqe
);
197 otc
.setStatus(ThreadContext::Halted
);