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44 #include "cpu/thread_context.hh"
46 #include "arch/kernel_stats.hh"
47 #include "base/misc.hh"
48 #include "base/trace.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/base.hh"
51 #include "cpu/quiesce_event.hh"
52 #include "debug/Context.hh"
53 #include "debug/Quiesce.hh"
54 #include "params/BaseCPU.hh"
55 #include "sim/full_system.hh"
58 ThreadContext::compare(ThreadContext
*one
, ThreadContext
*two
)
60 DPRINTF(Context
, "Comparing thread contexts\n");
62 // First loop through the integer registers.
63 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
64 TheISA::IntReg t1
= one
->readIntReg(i
);
65 TheISA::IntReg t2
= two
->readIntReg(i
);
67 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
71 // Then loop through the floating point registers.
72 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
73 TheISA::FloatRegBits t1
= one
->readFloatRegBits(i
);
74 TheISA::FloatRegBits t2
= two
->readFloatRegBits(i
);
76 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
80 // Then loop through the vector registers.
81 for (int i
= 0; i
< TheISA::NumVecRegs
; ++i
) {
82 RegId
rid(VecRegClass
, i
);
83 const TheISA::VecRegContainer
& t1
= one
->readVecReg(rid
);
84 const TheISA::VecRegContainer
& t2
= two
->readVecReg(rid
);
86 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
89 for (int i
= 0; i
< TheISA::NumMiscRegs
; ++i
) {
90 TheISA::MiscReg t1
= one
->readMiscRegNoEffect(i
);
91 TheISA::MiscReg t2
= two
->readMiscRegNoEffect(i
);
93 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
97 // loop through the Condition Code registers.
98 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
) {
99 TheISA::CCReg t1
= one
->readCCReg(i
);
100 TheISA::CCReg t2
= two
->readCCReg(i
);
102 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
105 if (!(one
->pcState() == two
->pcState()))
106 panic("PC state doesn't match.");
107 int id1
= one
->cpuId();
108 int id2
= two
->cpuId();
110 panic("CPU ids don't match, one: %d, two: %d", id1
, id2
);
112 const ContextID cid1
= one
->contextId();
113 const ContextID cid2
= two
->contextId();
115 panic("Context ids don't match, one: %d, two: %d", id1
, id2
);
121 ThreadContext::quiesce()
123 if (!getCpuPtr()->params()->do_quiesce
)
126 DPRINTF(Quiesce
, "%s: quiesce()\n", getCpuPtr()->name());
129 if (getKernelStats())
130 getKernelStats()->quiesce();
135 ThreadContext::quiesceTick(Tick resume
)
137 BaseCPU
*cpu
= getCpuPtr();
139 if (!cpu
->params()->do_quiesce
)
142 EndQuiesceEvent
*quiesceEvent
= getQuiesceEvent();
144 cpu
->reschedule(quiesceEvent
, resume
, true);
146 DPRINTF(Quiesce
, "%s: quiesceTick until %lu\n", cpu
->name(), resume
);
149 if (getKernelStats())
150 getKernelStats()->quiesce();
154 serialize(ThreadContext
&tc
, CheckpointOut
&cp
)
156 using namespace TheISA
;
158 FloatRegBits floatRegs
[NumFloatRegs
];
159 for (int i
= 0; i
< NumFloatRegs
; ++i
)
160 floatRegs
[i
] = tc
.readFloatRegBitsFlat(i
);
161 // This is a bit ugly, but needed to maintain backwards
163 arrayParamOut(cp
, "floatRegs.i", floatRegs
, NumFloatRegs
);
165 std::vector
<TheISA::VecRegContainer
> vecRegs(NumVecRegs
);
166 for (int i
= 0; i
< NumVecRegs
; ++i
) {
167 vecRegs
[i
] = tc
.readVecRegFlat(i
);
169 SERIALIZE_CONTAINER(vecRegs
);
171 IntReg intRegs
[NumIntRegs
];
172 for (int i
= 0; i
< NumIntRegs
; ++i
)
173 intRegs
[i
] = tc
.readIntRegFlat(i
);
174 SERIALIZE_ARRAY(intRegs
, NumIntRegs
);
176 #ifdef ISA_HAS_CC_REGS
177 CCReg ccRegs
[NumCCRegs
];
178 for (int i
= 0; i
< NumCCRegs
; ++i
)
179 ccRegs
[i
] = tc
.readCCRegFlat(i
);
180 SERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
183 tc
.pcState().serialize(cp
);
185 // thread_num and cpu_id are deterministic from the config
189 unserialize(ThreadContext
&tc
, CheckpointIn
&cp
)
191 using namespace TheISA
;
193 FloatRegBits floatRegs
[NumFloatRegs
];
194 // This is a bit ugly, but needed to maintain backwards
196 arrayParamIn(cp
, "floatRegs.i", floatRegs
, NumFloatRegs
);
197 for (int i
= 0; i
< NumFloatRegs
; ++i
)
198 tc
.setFloatRegBitsFlat(i
, floatRegs
[i
]);
200 std::vector
<TheISA::VecRegContainer
> vecRegs(NumVecRegs
);
201 UNSERIALIZE_CONTAINER(vecRegs
);
202 for (int i
= 0; i
< NumVecRegs
; ++i
) {
203 tc
.setVecRegFlat(i
, vecRegs
[i
]);
206 IntReg intRegs
[NumIntRegs
];
207 UNSERIALIZE_ARRAY(intRegs
, NumIntRegs
);
208 for (int i
= 0; i
< NumIntRegs
; ++i
)
209 tc
.setIntRegFlat(i
, intRegs
[i
]);
211 #ifdef ISA_HAS_CC_REGS
212 CCReg ccRegs
[NumCCRegs
];
213 UNSERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
214 for (int i
= 0; i
< NumCCRegs
; ++i
)
215 tc
.setCCRegFlat(i
, ccRegs
[i
]);
219 pcState
.unserialize(cp
);
222 // thread_num and cpu_id are deterministic from the config
226 takeOverFrom(ThreadContext
&ntc
, ThreadContext
&otc
)
228 assert(ntc
.getProcessPtr() == otc
.getProcessPtr());
230 ntc
.setStatus(otc
.status());
231 ntc
.copyArchRegs(&otc
);
232 ntc
.setContextId(otc
.contextId());
233 ntc
.setThreadId(otc
.threadId());
236 assert(ntc
.getSystemPtr() == otc
.getSystemPtr());
238 BaseCPU
*ncpu(ntc
.getCpuPtr());
240 EndQuiesceEvent
*oqe(otc
.getQuiesceEvent());
242 assert(oqe
->tc
== &otc
);
244 BaseCPU
*ocpu(otc
.getCpuPtr());
246 EndQuiesceEvent
*nqe(ntc
.getQuiesceEvent());
248 assert(nqe
->tc
== &ntc
);
250 if (oqe
->scheduled()) {
251 ncpu
->schedule(nqe
, oqe
->when());
252 ocpu
->deschedule(oqe
);
256 otc
.setStatus(ThreadContext::Halted
);