2 * Copyright (c) 2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "cpu/thread_context.hh"
44 #include "arch/generic/vec_pred_reg.hh"
45 #include "base/logging.hh"
46 #include "base/trace.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "debug/Context.hh"
50 #include "debug/Quiesce.hh"
51 #include "params/BaseCPU.hh"
52 #include "sim/full_system.hh"
55 ThreadContext::compare(ThreadContext
*one
, ThreadContext
*two
)
57 DPRINTF(Context
, "Comparing thread contexts\n");
59 // First loop through the integer registers.
60 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
61 RegVal t1
= one
->readIntReg(i
);
62 RegVal t2
= two
->readIntReg(i
);
64 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
68 // Then loop through the floating point registers.
69 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
70 RegVal t1
= one
->readFloatReg(i
);
71 RegVal t2
= two
->readFloatReg(i
);
73 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
77 // Then loop through the vector registers.
78 for (int i
= 0; i
< TheISA::NumVecRegs
; ++i
) {
79 RegId
rid(VecRegClass
, i
);
80 const TheISA::VecRegContainer
& t1
= one
->readVecReg(rid
);
81 const TheISA::VecRegContainer
& t2
= two
->readVecReg(rid
);
83 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
87 // Then loop through the predicate registers.
88 for (int i
= 0; i
< TheISA::NumVecPredRegs
; ++i
) {
89 RegId
rid(VecPredRegClass
, i
);
90 const TheISA::VecPredRegContainer
& t1
= one
->readVecPredReg(rid
);
91 const TheISA::VecPredRegContainer
& t2
= two
->readVecPredReg(rid
);
93 panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
97 for (int i
= 0; i
< TheISA::NumMiscRegs
; ++i
) {
98 RegVal t1
= one
->readMiscRegNoEffect(i
);
99 RegVal t2
= two
->readMiscRegNoEffect(i
);
101 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
105 // loop through the Condition Code registers.
106 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
) {
107 RegVal t1
= one
->readCCReg(i
);
108 RegVal t2
= two
->readCCReg(i
);
110 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
113 if (!(one
->pcState() == two
->pcState()))
114 panic("PC state doesn't match.");
115 int id1
= one
->cpuId();
116 int id2
= two
->cpuId();
118 panic("CPU ids don't match, one: %d, two: %d", id1
, id2
);
120 const ContextID cid1
= one
->contextId();
121 const ContextID cid2
= two
->contextId();
123 panic("Context ids don't match, one: %d, two: %d", id1
, id2
);
129 ThreadContext::quiesce()
131 getSystemPtr()->threads
.quiesce(contextId());
136 ThreadContext::quiesceTick(Tick resume
)
138 getSystemPtr()->threads
.quiesceTick(contextId(), resume
);
142 serialize(const ThreadContext
&tc
, CheckpointOut
&cp
)
144 RegVal floatRegs
[TheISA::NumFloatRegs
];
145 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
)
146 floatRegs
[i
] = tc
.readFloatRegFlat(i
);
147 // This is a bit ugly, but needed to maintain backwards
149 arrayParamOut(cp
, "floatRegs.i", floatRegs
, TheISA::NumFloatRegs
);
151 std::vector
<TheISA::VecRegContainer
> vecRegs(TheISA::NumVecRegs
);
152 for (int i
= 0; i
< TheISA::NumVecRegs
; ++i
) {
153 vecRegs
[i
] = tc
.readVecRegFlat(i
);
155 SERIALIZE_CONTAINER(vecRegs
);
157 std::vector
<TheISA::VecPredRegContainer
>
158 vecPredRegs(TheISA::NumVecPredRegs
);
159 for (int i
= 0; i
< TheISA::NumVecPredRegs
; ++i
) {
160 vecPredRegs
[i
] = tc
.readVecPredRegFlat(i
);
162 SERIALIZE_CONTAINER(vecPredRegs
);
164 RegVal intRegs
[TheISA::NumIntRegs
];
165 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
)
166 intRegs
[i
] = tc
.readIntRegFlat(i
);
167 SERIALIZE_ARRAY(intRegs
, TheISA::NumIntRegs
);
169 if (TheISA::NumCCRegs
) {
170 RegVal ccRegs
[TheISA::NumCCRegs
];
171 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
)
172 ccRegs
[i
] = tc
.readCCRegFlat(i
);
173 SERIALIZE_ARRAY(ccRegs
, TheISA::NumCCRegs
);
176 tc
.pcState().serialize(cp
);
178 // thread_num and cpu_id are deterministic from the config
182 unserialize(ThreadContext
&tc
, CheckpointIn
&cp
)
184 RegVal floatRegs
[TheISA::NumFloatRegs
];
185 // This is a bit ugly, but needed to maintain backwards
187 arrayParamIn(cp
, "floatRegs.i", floatRegs
, TheISA::NumFloatRegs
);
188 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
)
189 tc
.setFloatRegFlat(i
, floatRegs
[i
]);
191 std::vector
<TheISA::VecRegContainer
> vecRegs(TheISA::NumVecRegs
);
192 UNSERIALIZE_CONTAINER(vecRegs
);
193 for (int i
= 0; i
< TheISA::NumVecRegs
; ++i
) {
194 tc
.setVecRegFlat(i
, vecRegs
[i
]);
197 std::vector
<TheISA::VecPredRegContainer
>
198 vecPredRegs(TheISA::NumVecPredRegs
);
199 UNSERIALIZE_CONTAINER(vecPredRegs
);
200 for (int i
= 0; i
< TheISA::NumVecPredRegs
; ++i
) {
201 tc
.setVecPredRegFlat(i
, vecPredRegs
[i
]);
204 RegVal intRegs
[TheISA::NumIntRegs
];
205 UNSERIALIZE_ARRAY(intRegs
, TheISA::NumIntRegs
);
206 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
)
207 tc
.setIntRegFlat(i
, intRegs
[i
]);
209 if (TheISA::NumCCRegs
) {
210 RegVal ccRegs
[TheISA::NumCCRegs
];
211 UNSERIALIZE_ARRAY(ccRegs
, TheISA::NumCCRegs
);
212 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
)
213 tc
.setCCRegFlat(i
, ccRegs
[i
]);
216 TheISA::PCState pcState
;
217 pcState
.unserialize(cp
);
220 // thread_num and cpu_id are deterministic from the config
224 takeOverFrom(ThreadContext
&ntc
, ThreadContext
&otc
)
226 assert(ntc
.getProcessPtr() == otc
.getProcessPtr());
228 ntc
.setStatus(otc
.status());
229 ntc
.copyArchRegs(&otc
);
230 ntc
.setContextId(otc
.contextId());
231 ntc
.setThreadId(otc
.threadId());
234 assert(ntc
.getSystemPtr() == otc
.getSystemPtr());
236 otc
.setStatus(ThreadContext::Halted
);