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43 #include "base/misc.hh"
44 #include "base/trace.hh"
45 #include "config/the_isa.hh"
46 #include "cpu/base.hh"
47 #include "cpu/quiesce_event.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Context.hh"
50 #include "sim/full_system.hh"
53 ThreadContext::compare(ThreadContext
*one
, ThreadContext
*two
)
55 DPRINTF(Context
, "Comparing thread contexts\n");
57 // First loop through the integer registers.
58 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
59 TheISA::IntReg t1
= one
->readIntReg(i
);
60 TheISA::IntReg t2
= two
->readIntReg(i
);
62 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
66 // Then loop through the floating point registers.
67 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
68 TheISA::FloatRegBits t1
= one
->readFloatRegBits(i
);
69 TheISA::FloatRegBits t2
= two
->readFloatRegBits(i
);
71 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
74 for (int i
= 0; i
< TheISA::NumMiscRegs
; ++i
) {
75 TheISA::MiscReg t1
= one
->readMiscRegNoEffect(i
);
76 TheISA::MiscReg t2
= two
->readMiscRegNoEffect(i
);
78 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
82 if (!(one
->pcState() == two
->pcState()))
83 panic("PC state doesn't match.");
84 int id1
= one
->cpuId();
85 int id2
= two
->cpuId();
87 panic("CPU ids don't match, one: %d, two: %d", id1
, id2
);
89 id1
= one
->contextId();
90 id2
= two
->contextId();
92 panic("Context ids don't match, one: %d, two: %d", id1
, id2
);
98 serialize(ThreadContext
&tc
, std::ostream
&os
)
100 using namespace TheISA
;
102 FloatRegBits floatRegs
[NumFloatRegs
];
103 for (int i
= 0; i
< NumFloatRegs
; ++i
)
104 floatRegs
[i
] = tc
.readFloatRegBitsFlat(i
);
105 // This is a bit ugly, but needed to maintain backwards
107 arrayParamOut(os
, "floatRegs.i", floatRegs
, NumFloatRegs
);
109 IntReg intRegs
[NumIntRegs
];
110 for (int i
= 0; i
< NumIntRegs
; ++i
)
111 intRegs
[i
] = tc
.readIntRegFlat(i
);
112 SERIALIZE_ARRAY(intRegs
, NumIntRegs
);
114 tc
.pcState().serialize(os
);
116 // thread_num and cpu_id are deterministic from the config
120 unserialize(ThreadContext
&tc
, Checkpoint
*cp
, const std::string
§ion
)
122 using namespace TheISA
;
124 FloatRegBits floatRegs
[NumFloatRegs
];
125 // This is a bit ugly, but needed to maintain backwards
127 arrayParamIn(cp
, section
, "floatRegs.i", floatRegs
, NumFloatRegs
);
128 for (int i
= 0; i
< NumFloatRegs
; ++i
)
129 tc
.setFloatRegBitsFlat(i
, floatRegs
[i
]);
131 IntReg intRegs
[NumIntRegs
];
132 UNSERIALIZE_ARRAY(intRegs
, NumIntRegs
);
133 for (int i
= 0; i
< NumIntRegs
; ++i
)
134 tc
.setIntRegFlat(i
, intRegs
[i
]);
137 pcState
.unserialize(cp
, section
);
140 // thread_num and cpu_id are deterministic from the config
144 takeOverFrom(ThreadContext
&ntc
, ThreadContext
&otc
)
146 assert(ntc
.getProcessPtr() == otc
.getProcessPtr());
148 ntc
.setStatus(otc
.status());
149 ntc
.copyArchRegs(&otc
);
150 ntc
.setContextId(otc
.contextId());
151 ntc
.setThreadId(otc
.threadId());
154 assert(ntc
.getSystemPtr() == otc
.getSystemPtr());
156 BaseCPU
*ncpu(ntc
.getCpuPtr());
158 EndQuiesceEvent
*oqe(otc
.getQuiesceEvent());
160 assert(oqe
->tc
== &otc
);
162 BaseCPU
*ocpu(otc
.getCpuPtr());
164 EndQuiesceEvent
*nqe(ntc
.getQuiesceEvent());
166 assert(nqe
->tc
== &ntc
);
168 if (oqe
->scheduled()) {
169 ncpu
->schedule(nqe
, oqe
->when());
170 ocpu
->deschedule(oqe
);
174 otc
.setStatus(ThreadContext::Halted
);