src/cpu/thread_context.cc

   1 /*
   2  * Copyright (c) 2012, 2016-2017 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "cpu/thread_context.hh"
  43
  44 #include "arch/generic/vec_pred_reg.hh"
  45 #include "base/logging.hh"
  46 #include "base/trace.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/base.hh"
  49 #include "debug/Context.hh"
  50 #include "debug/Quiesce.hh"
  51 #include "params/BaseCPU.hh"
  52 #include "sim/full_system.hh"
  53
  54 void
  55 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
  56 {
  57     DPRINTF(Context, "Comparing thread contexts\n");
  58
  59     // First loop through the integer registers.
  60     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
  61         RegVal t1 = one->readIntReg(i);
  62         RegVal t2 = two->readIntReg(i);
  63         if (t1 != t2)
  64             panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
  65                   i, t1, t2);
  66     }
  67
  68     // Then loop through the floating point registers.
  69     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
  70         RegVal t1 = one->readFloatReg(i);
  71         RegVal t2 = two->readFloatReg(i);
  72         if (t1 != t2)
  73             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
  74                   i, t1, t2);
  75     }
  76
  77     // Then loop through the vector registers.
  78     for (int i = 0; i < TheISA::NumVecRegs; ++i) {
  79         RegId rid(VecRegClass, i);
  80         const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
  81         const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
  82         if (t1 != t2)
  83             panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
  84                   i, t1, t2);
  85     }
  86
  87     // Then loop through the predicate registers.
  88     for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
  89         RegId rid(VecPredRegClass, i);
  90         const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
  91         const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
  92         if (t1 != t2)
  93             panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
  94                   i, t1, t2);
  95     }
  96
  97     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
  98         RegVal t1 = one->readMiscRegNoEffect(i);
  99         RegVal t2 = two->readMiscRegNoEffect(i);
 100         if (t1 != t2)
 101             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
 102                   i, t1, t2);
 103     }
 104
 105     // loop through the Condition Code registers.
 106     for (int i = 0; i < TheISA::NumCCRegs; ++i) {
 107         RegVal t1 = one->readCCReg(i);
 108         RegVal t2 = two->readCCReg(i);
 109         if (t1 != t2)
 110             panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
 111                   i, t1, t2);
 112     }
 113     if (!(one->pcState() == two->pcState()))
 114         panic("PC state doesn't match.");
 115     int id1 = one->cpuId();
 116     int id2 = two->cpuId();
 117     if (id1 != id2)
 118         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
 119
 120     const ContextID cid1 = one->contextId();
 121     const ContextID cid2 = two->contextId();
 122     if (cid1 != cid2)
 123         panic("Context ids don't match, one: %d, two: %d", id1, id2);
 124
 125
 126 }
 127
 128 void
 129 ThreadContext::quiesce()
 130 {
 131     getSystemPtr()->threads.quiesce(contextId());
 132 }
 133
 134
 135 void
 136 ThreadContext::quiesceTick(Tick resume)
 137 {
 138     getSystemPtr()->threads.quiesceTick(contextId(), resume);
 139 }
 140
 141 void
 142 serialize(const ThreadContext &tc, CheckpointOut &cp)
 143 {
 144     using namespace TheISA;
 145
 146     RegVal floatRegs[NumFloatRegs];
 147     for (int i = 0; i < NumFloatRegs; ++i)
 148         floatRegs[i] = tc.readFloatRegFlat(i);
 149     // This is a bit ugly, but needed to maintain backwards
 150     // compatibility.
 151     arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 152
 153     std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
 154     for (int i = 0; i < NumVecRegs; ++i) {
 155         vecRegs[i] = tc.readVecRegFlat(i);
 156     }
 157     SERIALIZE_CONTAINER(vecRegs);
 158
 159     std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
 160     for (int i = 0; i < NumVecPredRegs; ++i) {
 161         vecPredRegs[i] = tc.readVecPredRegFlat(i);
 162     }
 163     SERIALIZE_CONTAINER(vecPredRegs);
 164
 165     RegVal intRegs[NumIntRegs];
 166     for (int i = 0; i < NumIntRegs; ++i)
 167         intRegs[i] = tc.readIntRegFlat(i);
 168     SERIALIZE_ARRAY(intRegs, NumIntRegs);
 169
 170     if (NumCCRegs) {
 171         RegVal ccRegs[NumCCRegs];
 172         for (int i = 0; i < NumCCRegs; ++i)
 173             ccRegs[i] = tc.readCCRegFlat(i);
 174         SERIALIZE_ARRAY(ccRegs, NumCCRegs);
 175     }
 176
 177     tc.pcState().serialize(cp);
 178
 179     // thread_num and cpu_id are deterministic from the config
 180 }
 181
 182 void
 183 unserialize(ThreadContext &tc, CheckpointIn &cp)
 184 {
 185     using namespace TheISA;
 186
 187     RegVal floatRegs[NumFloatRegs];
 188     // This is a bit ugly, but needed to maintain backwards
 189     // compatibility.
 190     arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 191     for (int i = 0; i < NumFloatRegs; ++i)
 192         tc.setFloatRegFlat(i, floatRegs[i]);
 193
 194     std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
 195     UNSERIALIZE_CONTAINER(vecRegs);
 196     for (int i = 0; i < NumVecRegs; ++i) {
 197         tc.setVecRegFlat(i, vecRegs[i]);
 198     }
 199
 200     std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
 201     UNSERIALIZE_CONTAINER(vecPredRegs);
 202     for (int i = 0; i < NumVecPredRegs; ++i) {
 203         tc.setVecPredRegFlat(i, vecPredRegs[i]);
 204     }
 205
 206     RegVal intRegs[NumIntRegs];
 207     UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
 208     for (int i = 0; i < NumIntRegs; ++i)
 209         tc.setIntRegFlat(i, intRegs[i]);
 210
 211     if (NumCCRegs) {
 212         RegVal ccRegs[NumCCRegs];
 213         UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
 214         for (int i = 0; i < NumCCRegs; ++i)
 215             tc.setCCRegFlat(i, ccRegs[i]);
 216     }
 217
 218     PCState pcState;
 219     pcState.unserialize(cp);
 220     tc.pcState(pcState);
 221
 222     // thread_num and cpu_id are deterministic from the config
 223 }
 224
 225 void
 226 takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
 227 {
 228     assert(ntc.getProcessPtr() == otc.getProcessPtr());
 229
 230     ntc.setStatus(otc.status());
 231     ntc.copyArchRegs(&otc);
 232     ntc.setContextId(otc.contextId());
 233     ntc.setThreadId(otc.threadId());
 234
 235     if (FullSystem)
 236         assert(ntc.getSystemPtr() == otc.getSystemPtr());
 237
 238     otc.setStatus(ThreadContext::Halted);
 239 }