src/cpu/thread_context.cc

   1 /*
   2  * Copyright (c) 2012, 2016-2017 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "cpu/thread_context.hh"
  43
  44 #include "arch/generic/vec_pred_reg.hh"
  45 #include "base/logging.hh"
  46 #include "base/trace.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/base.hh"
  49 #include "cpu/quiesce_event.hh"
  50 #include "debug/Context.hh"
  51 #include "debug/Quiesce.hh"
  52 #include "kern/kernel_stats.hh"
  53 #include "params/BaseCPU.hh"
  54 #include "sim/full_system.hh"
  55
  56 void
  57 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
  58 {
  59     DPRINTF(Context, "Comparing thread contexts\n");
  60
  61     // First loop through the integer registers.
  62     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
  63         RegVal t1 = one->readIntReg(i);
  64         RegVal t2 = two->readIntReg(i);
  65         if (t1 != t2)
  66             panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
  67                   i, t1, t2);
  68     }
  69
  70     // Then loop through the floating point registers.
  71     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
  72         RegVal t1 = one->readFloatReg(i);
  73         RegVal t2 = two->readFloatReg(i);
  74         if (t1 != t2)
  75             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
  76                   i, t1, t2);
  77     }
  78
  79     // Then loop through the vector registers.
  80     for (int i = 0; i < TheISA::NumVecRegs; ++i) {
  81         RegId rid(VecRegClass, i);
  82         const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
  83         const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
  84         if (t1 != t2)
  85             panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
  86                   i, t1, t2);
  87     }
  88
  89     // Then loop through the predicate registers.
  90     for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
  91         RegId rid(VecPredRegClass, i);
  92         const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
  93         const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
  94         if (t1 != t2)
  95             panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
  96                   i, t1, t2);
  97     }
  98
  99     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
 100         RegVal t1 = one->readMiscRegNoEffect(i);
 101         RegVal t2 = two->readMiscRegNoEffect(i);
 102         if (t1 != t2)
 103             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
 104                   i, t1, t2);
 105     }
 106
 107     // loop through the Condition Code registers.
 108     for (int i = 0; i < TheISA::NumCCRegs; ++i) {
 109         RegVal t1 = one->readCCReg(i);
 110         RegVal t2 = two->readCCReg(i);
 111         if (t1 != t2)
 112             panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
 113                   i, t1, t2);
 114     }
 115     if (!(one->pcState() == two->pcState()))
 116         panic("PC state doesn't match.");
 117     int id1 = one->cpuId();
 118     int id2 = two->cpuId();
 119     if (id1 != id2)
 120         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
 121
 122     const ContextID cid1 = one->contextId();
 123     const ContextID cid2 = two->contextId();
 124     if (cid1 != cid2)
 125         panic("Context ids don't match, one: %d, two: %d", id1, id2);
 126
 127
 128 }
 129
 130 void
 131 ThreadContext::quiesce()
 132 {
 133     if (!getCpuPtr()->params()->do_quiesce)
 134         return;
 135
 136     DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
 137
 138     suspend();
 139     if (getKernelStats())
 140         getKernelStats()->quiesce();
 141 }
 142
 143
 144 void
 145 ThreadContext::quiesceTick(Tick resume)
 146 {
 147     BaseCPU *cpu = getCpuPtr();
 148
 149     if (!cpu->params()->do_quiesce)
 150         return;
 151
 152     EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
 153
 154     cpu->reschedule(quiesceEvent, resume, true);
 155
 156     DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
 157
 158     suspend();
 159     if (getKernelStats())
 160         getKernelStats()->quiesce();
 161 }
 162
 163 void
 164 serialize(const ThreadContext &tc, CheckpointOut &cp)
 165 {
 166     using namespace TheISA;
 167
 168     RegVal floatRegs[NumFloatRegs];
 169     for (int i = 0; i < NumFloatRegs; ++i)
 170         floatRegs[i] = tc.readFloatRegFlat(i);
 171     // This is a bit ugly, but needed to maintain backwards
 172     // compatibility.
 173     arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 174
 175     std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
 176     for (int i = 0; i < NumVecRegs; ++i) {
 177         vecRegs[i] = tc.readVecRegFlat(i);
 178     }
 179     SERIALIZE_CONTAINER(vecRegs);
 180
 181     std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
 182     for (int i = 0; i < NumVecPredRegs; ++i) {
 183         vecPredRegs[i] = tc.readVecPredRegFlat(i);
 184     }
 185     SERIALIZE_CONTAINER(vecPredRegs);
 186
 187     RegVal intRegs[NumIntRegs];
 188     for (int i = 0; i < NumIntRegs; ++i)
 189         intRegs[i] = tc.readIntRegFlat(i);
 190     SERIALIZE_ARRAY(intRegs, NumIntRegs);
 191
 192     if (NumCCRegs) {
 193         RegVal ccRegs[NumCCRegs];
 194         for (int i = 0; i < NumCCRegs; ++i)
 195             ccRegs[i] = tc.readCCRegFlat(i);
 196         SERIALIZE_ARRAY(ccRegs, NumCCRegs);
 197     }
 198
 199     tc.pcState().serialize(cp);
 200
 201     // thread_num and cpu_id are deterministic from the config
 202 }
 203
 204 void
 205 unserialize(ThreadContext &tc, CheckpointIn &cp)
 206 {
 207     using namespace TheISA;
 208
 209     RegVal floatRegs[NumFloatRegs];
 210     // This is a bit ugly, but needed to maintain backwards
 211     // compatibility.
 212     arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 213     for (int i = 0; i < NumFloatRegs; ++i)
 214         tc.setFloatRegFlat(i, floatRegs[i]);
 215
 216     std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
 217     UNSERIALIZE_CONTAINER(vecRegs);
 218     for (int i = 0; i < NumVecRegs; ++i) {
 219         tc.setVecRegFlat(i, vecRegs[i]);
 220     }
 221
 222     std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
 223     UNSERIALIZE_CONTAINER(vecPredRegs);
 224     for (int i = 0; i < NumVecPredRegs; ++i) {
 225         tc.setVecPredRegFlat(i, vecPredRegs[i]);
 226     }
 227
 228     RegVal intRegs[NumIntRegs];
 229     UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
 230     for (int i = 0; i < NumIntRegs; ++i)
 231         tc.setIntRegFlat(i, intRegs[i]);
 232
 233     if (NumCCRegs) {
 234         RegVal ccRegs[NumCCRegs];
 235         UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
 236         for (int i = 0; i < NumCCRegs; ++i)
 237             tc.setCCRegFlat(i, ccRegs[i]);
 238     }
 239
 240     PCState pcState;
 241     pcState.unserialize(cp);
 242     tc.pcState(pcState);
 243
 244     // thread_num and cpu_id are deterministic from the config
 245 }
 246
 247 void
 248 takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
 249 {
 250     assert(ntc.getProcessPtr() == otc.getProcessPtr());
 251
 252     ntc.setStatus(otc.status());
 253     ntc.copyArchRegs(&otc);
 254     ntc.setContextId(otc.contextId());
 255     ntc.setThreadId(otc.threadId());
 256
 257     if (FullSystem) {
 258         assert(ntc.getSystemPtr() == otc.getSystemPtr());
 259
 260         BaseCPU *ncpu(ntc.getCpuPtr());
 261         assert(ncpu);
 262         EndQuiesceEvent *oqe(otc.getQuiesceEvent());
 263         assert(oqe);
 264         assert(oqe->tc == &otc);
 265
 266         BaseCPU *ocpu(otc.getCpuPtr());
 267         assert(ocpu);
 268         EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
 269         assert(nqe);
 270         assert(nqe->tc == &ntc);
 271
 272         if (oqe->scheduled()) {
 273             ncpu->schedule(nqe, oqe->when());
 274             ocpu->deschedule(oqe);
 275         }
 276     }
 277
 278     otc.setStatus(ThreadContext::Halted);
 279 }