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44 #include "cpu/thread_context.hh"
46 #include "arch/generic/vec_pred_reg.hh"
47 #include "arch/kernel_stats.hh"
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/base.hh"
52 #include "cpu/quiesce_event.hh"
53 #include "debug/Context.hh"
54 #include "debug/Quiesce.hh"
55 #include "params/BaseCPU.hh"
56 #include "sim/full_system.hh"
59 ThreadContext::compare(ThreadContext
*one
, ThreadContext
*two
)
61 DPRINTF(Context
, "Comparing thread contexts\n");
63 // First loop through the integer registers.
64 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
65 RegVal t1
= one
->readIntReg(i
);
66 RegVal t2
= two
->readIntReg(i
);
68 panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
72 // Then loop through the floating point registers.
73 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
74 RegVal t1
= one
->readFloatReg(i
);
75 RegVal t2
= two
->readFloatReg(i
);
77 panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
81 // Then loop through the vector registers.
82 for (int i
= 0; i
< TheISA::NumVecRegs
; ++i
) {
83 RegId
rid(VecRegClass
, i
);
84 const TheISA::VecRegContainer
& t1
= one
->readVecReg(rid
);
85 const TheISA::VecRegContainer
& t2
= two
->readVecReg(rid
);
87 panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
91 // Then loop through the predicate registers.
92 for (int i
= 0; i
< TheISA::NumVecPredRegs
; ++i
) {
93 RegId
rid(VecPredRegClass
, i
);
94 const TheISA::VecPredRegContainer
& t1
= one
->readVecPredReg(rid
);
95 const TheISA::VecPredRegContainer
& t2
= two
->readVecPredReg(rid
);
97 panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
101 for (int i
= 0; i
< TheISA::NumMiscRegs
; ++i
) {
102 RegVal t1
= one
->readMiscRegNoEffect(i
);
103 RegVal t2
= two
->readMiscRegNoEffect(i
);
105 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
109 // loop through the Condition Code registers.
110 for (int i
= 0; i
< TheISA::NumCCRegs
; ++i
) {
111 TheISA::CCReg t1
= one
->readCCReg(i
);
112 TheISA::CCReg t2
= two
->readCCReg(i
);
114 panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
117 if (!(one
->pcState() == two
->pcState()))
118 panic("PC state doesn't match.");
119 int id1
= one
->cpuId();
120 int id2
= two
->cpuId();
122 panic("CPU ids don't match, one: %d, two: %d", id1
, id2
);
124 const ContextID cid1
= one
->contextId();
125 const ContextID cid2
= two
->contextId();
127 panic("Context ids don't match, one: %d, two: %d", id1
, id2
);
133 ThreadContext::quiesce()
135 if (!getCpuPtr()->params()->do_quiesce
)
138 DPRINTF(Quiesce
, "%s: quiesce()\n", getCpuPtr()->name());
141 if (getKernelStats())
142 getKernelStats()->quiesce();
147 ThreadContext::quiesceTick(Tick resume
)
149 BaseCPU
*cpu
= getCpuPtr();
151 if (!cpu
->params()->do_quiesce
)
154 EndQuiesceEvent
*quiesceEvent
= getQuiesceEvent();
156 cpu
->reschedule(quiesceEvent
, resume
, true);
158 DPRINTF(Quiesce
, "%s: quiesceTick until %lu\n", cpu
->name(), resume
);
161 if (getKernelStats())
162 getKernelStats()->quiesce();
166 serialize(ThreadContext
&tc
, CheckpointOut
&cp
)
168 using namespace TheISA
;
170 RegVal floatRegs
[NumFloatRegs
];
171 for (int i
= 0; i
< NumFloatRegs
; ++i
)
172 floatRegs
[i
] = tc
.readFloatRegFlat(i
);
173 // This is a bit ugly, but needed to maintain backwards
175 arrayParamOut(cp
, "floatRegs.i", floatRegs
, NumFloatRegs
);
177 std::vector
<TheISA::VecRegContainer
> vecRegs(NumVecRegs
);
178 for (int i
= 0; i
< NumVecRegs
; ++i
) {
179 vecRegs
[i
] = tc
.readVecRegFlat(i
);
181 SERIALIZE_CONTAINER(vecRegs
);
183 std::vector
<TheISA::VecPredRegContainer
> vecPredRegs(NumVecPredRegs
);
184 for (int i
= 0; i
< NumVecPredRegs
; ++i
) {
185 vecPredRegs
[i
] = tc
.readVecPredRegFlat(i
);
187 SERIALIZE_CONTAINER(vecPredRegs
);
189 RegVal intRegs
[NumIntRegs
];
190 for (int i
= 0; i
< NumIntRegs
; ++i
)
191 intRegs
[i
] = tc
.readIntRegFlat(i
);
192 SERIALIZE_ARRAY(intRegs
, NumIntRegs
);
194 #ifdef ISA_HAS_CC_REGS
195 CCReg ccRegs
[NumCCRegs
];
196 for (int i
= 0; i
< NumCCRegs
; ++i
)
197 ccRegs
[i
] = tc
.readCCRegFlat(i
);
198 SERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
201 tc
.pcState().serialize(cp
);
203 // thread_num and cpu_id are deterministic from the config
207 unserialize(ThreadContext
&tc
, CheckpointIn
&cp
)
209 using namespace TheISA
;
211 RegVal floatRegs
[NumFloatRegs
];
212 // This is a bit ugly, but needed to maintain backwards
214 arrayParamIn(cp
, "floatRegs.i", floatRegs
, NumFloatRegs
);
215 for (int i
= 0; i
< NumFloatRegs
; ++i
)
216 tc
.setFloatRegFlat(i
, floatRegs
[i
]);
218 std::vector
<TheISA::VecRegContainer
> vecRegs(NumVecRegs
);
219 UNSERIALIZE_CONTAINER(vecRegs
);
220 for (int i
= 0; i
< NumVecRegs
; ++i
) {
221 tc
.setVecRegFlat(i
, vecRegs
[i
]);
224 std::vector
<TheISA::VecPredRegContainer
> vecPredRegs(NumVecPredRegs
);
225 UNSERIALIZE_CONTAINER(vecPredRegs
);
226 for (int i
= 0; i
< NumVecPredRegs
; ++i
) {
227 tc
.setVecPredRegFlat(i
, vecPredRegs
[i
]);
230 RegVal intRegs
[NumIntRegs
];
231 UNSERIALIZE_ARRAY(intRegs
, NumIntRegs
);
232 for (int i
= 0; i
< NumIntRegs
; ++i
)
233 tc
.setIntRegFlat(i
, intRegs
[i
]);
235 #ifdef ISA_HAS_CC_REGS
236 CCReg ccRegs
[NumCCRegs
];
237 UNSERIALIZE_ARRAY(ccRegs
, NumCCRegs
);
238 for (int i
= 0; i
< NumCCRegs
; ++i
)
239 tc
.setCCRegFlat(i
, ccRegs
[i
]);
243 pcState
.unserialize(cp
);
246 // thread_num and cpu_id are deterministic from the config
250 takeOverFrom(ThreadContext
&ntc
, ThreadContext
&otc
)
252 assert(ntc
.getProcessPtr() == otc
.getProcessPtr());
254 ntc
.setStatus(otc
.status());
255 ntc
.copyArchRegs(&otc
);
256 ntc
.setContextId(otc
.contextId());
257 ntc
.setThreadId(otc
.threadId());
260 assert(ntc
.getSystemPtr() == otc
.getSystemPtr());
262 BaseCPU
*ncpu(ntc
.getCpuPtr());
264 EndQuiesceEvent
*oqe(otc
.getQuiesceEvent());
266 assert(oqe
->tc
== &otc
);
268 BaseCPU
*ocpu(otc
.getCpuPtr());
270 EndQuiesceEvent
*nqe(ntc
.getQuiesceEvent());
272 assert(nqe
->tc
== &ntc
);
274 if (oqe
->scheduled()) {
275 ncpu
->schedule(nqe
, oqe
->when());
276 ocpu
->deschedule(oqe
);
280 otc
.setStatus(ThreadContext::Halted
);