src/cpu/thread_context.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #include "base/misc.hh"
  45 #include "base/trace.hh"
  46 #include "config/the_isa.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/quiesce_event.hh"
  49 #include "cpu/thread_context.hh"
  50 #include "debug/Context.hh"
  51 #include "sim/full_system.hh"
  52
  53 void
  54 ThreadContext::compare(ThreadContext *one, ThreadContext *two)
  55 {
  56     DPRINTF(Context, "Comparing thread contexts\n");
  57
  58     // First loop through the integer registers.
  59     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
  60         TheISA::IntReg t1 = one->readIntReg(i);
  61         TheISA::IntReg t2 = two->readIntReg(i);
  62         if (t1 != t2)
  63             panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
  64                   i, t1, t2);
  65     }
  66
  67     // Then loop through the floating point registers.
  68     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
  69         TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
  70         TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
  71         if (t1 != t2)
  72             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
  73                   i, t1, t2);
  74     }
  75     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
  76         TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
  77         TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
  78         if (t1 != t2)
  79             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
  80                   i, t1, t2);
  81     }
  82
  83     // loop through the Condition Code registers.
  84     for (int i = 0; i < TheISA::NumCCRegs; ++i) {
  85         TheISA::CCReg t1 = one->readCCReg(i);
  86         TheISA::CCReg t2 = two->readCCReg(i);
  87         if (t1 != t2)
  88             panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
  89                   i, t1, t2);
  90     }
  91     if (!(one->pcState() == two->pcState()))
  92         panic("PC state doesn't match.");
  93     int id1 = one->cpuId();
  94     int id2 = two->cpuId();
  95     if (id1 != id2)
  96         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
  97
  98     id1 = one->contextId();
  99     id2 = two->contextId();
 100     if (id1 != id2)
 101         panic("Context ids don't match, one: %d, two: %d", id1, id2);
 102
 103
 104 }
 105
 106 void
 107 serialize(ThreadContext &tc, CheckpointOut &cp)
 108 {
 109     using namespace TheISA;
 110
 111     FloatRegBits floatRegs[NumFloatRegs];
 112     for (int i = 0; i < NumFloatRegs; ++i)
 113         floatRegs[i] = tc.readFloatRegBitsFlat(i);
 114     // This is a bit ugly, but needed to maintain backwards
 115     // compatibility.
 116     arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 117
 118     IntReg intRegs[NumIntRegs];
 119     for (int i = 0; i < NumIntRegs; ++i)
 120         intRegs[i] = tc.readIntRegFlat(i);
 121     SERIALIZE_ARRAY(intRegs, NumIntRegs);
 122
 123 #ifdef ISA_HAS_CC_REGS
 124     CCReg ccRegs[NumCCRegs];
 125     for (int i = 0; i < NumCCRegs; ++i)
 126         ccRegs[i] = tc.readCCRegFlat(i);
 127     SERIALIZE_ARRAY(ccRegs, NumCCRegs);
 128 #endif
 129
 130     tc.pcState().serialize(cp);
 131
 132     // thread_num and cpu_id are deterministic from the config
 133 }
 134
 135 void
 136 unserialize(ThreadContext &tc, CheckpointIn &cp)
 137 {
 138     using namespace TheISA;
 139
 140     FloatRegBits floatRegs[NumFloatRegs];
 141     // This is a bit ugly, but needed to maintain backwards
 142     // compatibility.
 143     arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
 144     for (int i = 0; i < NumFloatRegs; ++i)
 145         tc.setFloatRegBitsFlat(i, floatRegs[i]);
 146
 147     IntReg intRegs[NumIntRegs];
 148     UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
 149     for (int i = 0; i < NumIntRegs; ++i)
 150         tc.setIntRegFlat(i, intRegs[i]);
 151
 152 #ifdef ISA_HAS_CC_REGS
 153     CCReg ccRegs[NumCCRegs];
 154     UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
 155     for (int i = 0; i < NumCCRegs; ++i)
 156         tc.setCCRegFlat(i, ccRegs[i]);
 157 #endif
 158
 159     PCState pcState;
 160     pcState.unserialize(cp);
 161     tc.pcState(pcState);
 162
 163     // thread_num and cpu_id are deterministic from the config
 164 }
 165
 166 void
 167 takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
 168 {
 169     assert(ntc.getProcessPtr() == otc.getProcessPtr());
 170
 171     ntc.setStatus(otc.status());
 172     ntc.copyArchRegs(&otc);
 173     ntc.setContextId(otc.contextId());
 174     ntc.setThreadId(otc.threadId());
 175
 176     if (FullSystem) {
 177         assert(ntc.getSystemPtr() == otc.getSystemPtr());
 178
 179         BaseCPU *ncpu(ntc.getCpuPtr());
 180         assert(ncpu);
 181         EndQuiesceEvent *oqe(otc.getQuiesceEvent());
 182         assert(oqe);
 183         assert(oqe->tc == &otc);
 184
 185         BaseCPU *ocpu(otc.getCpuPtr());
 186         assert(ocpu);
 187         EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
 188         assert(nqe);
 189         assert(nqe->tc == &ntc);
 190
 191         if (oqe->scheduled()) {
 192             ncpu->schedule(nqe, oqe->when());
 193             ocpu->deschedule(oqe);
 194         }
 195     }
 196
 197     otc.setStatus(ThreadContext::Halted);
 198 }