src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include "arch/regfile.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "mem/request.hh"
  38 #include "sim/faults.hh"
  39 #include "sim/host.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/syscallreturn.hh"
  42 #include "sim/byteswap.hh"
  43
  44 // @todo: Figure out a more architecture independent way to obtain the ITB and
  45 // DTB pointers.
  46 namespace TheISA
  47 {
  48     class DTB;
  49     class ITB;
  50 }
  51 class BaseCPU;
  52 class EndQuiesceEvent;
  53 class Event;
  54 class TranslatingPort;
  55 class FunctionalPort;
  56 class VirtualPort;
  57 class Process;
  58 class System;
  59 namespace TheISA {
  60     namespace Kernel {
  61         class Statistics;
  62     };
  63 };
  64
  65 /**
  66  * ThreadContext is the external interface to all thread state for
  67  * anything outside of the CPU. It provides all accessor methods to
  68  * state that might be needed by external objects, ranging from
  69  * register values to things such as kernel stats. It is an abstract
  70  * base class; the CPU can create its own ThreadContext by either
  71  * deriving from it, or using the templated ProxyThreadContext.
  72  *
  73  * The ThreadContext is slightly different than the ExecContext.  The
  74  * ThreadContext provides access to an individual thread's state; an
  75  * ExecContext provides ISA access to the CPU (meaning it is
  76  * implicitly multithreaded on SMT systems).  Additionally the
  77  * ThreadState is an abstract class that exactly defines the
  78  * interface; the ExecContext is a more implicit interface that must
  79  * be implemented so that the ISA can access whatever state it needs.
  80  */
  81 class ThreadContext
  82 {
  83   protected:
  84     typedef TheISA::RegFile RegFile;
  85     typedef TheISA::MachInst MachInst;
  86     typedef TheISA::IntReg IntReg;
  87     typedef TheISA::FloatReg FloatReg;
  88     typedef TheISA::FloatRegBits FloatRegBits;
  89     typedef TheISA::MiscRegFile MiscRegFile;
  90     typedef TheISA::MiscReg MiscReg;
  91   public:
  92     enum Status
  93     {
  94         /// Initialized but not running yet.  All CPUs start in
  95         /// this state, but most transition to Active on cycle 1.
  96         /// In MP or SMT systems, non-primary contexts will stay
  97         /// in this state until a thread is assigned to them.
  98         Unallocated,
  99
 100         /// Running.  Instructions should be executed only when
 101         /// the context is in this state.
 102         Active,
 103
 104         /// Temporarily inactive.  Entered while waiting for
 105         /// synchronization, etc.
 106         Suspended,
 107
 108         /// Permanently shut down.  Entered when target executes
 109         /// m5exit pseudo-instruction.  When all contexts enter
 110         /// this state, the simulation will terminate.
 111         Halted
 112     };
 113
 114     virtual ~ThreadContext() { };
 115
 116     virtual BaseCPU *getCpuPtr() = 0;
 117
 118     virtual void setCpuId(int id) = 0;
 119
 120     virtual int readCpuId() = 0;
 121
 122 #if FULL_SYSTEM
 123     virtual System *getSystemPtr() = 0;
 124
 125     virtual TheISA::ITB *getITBPtr() = 0;
 126
 127     virtual TheISA::DTB *getDTBPtr() = 0;
 128
 129     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 130
 131     virtual FunctionalPort *getPhysPort() = 0;
 132
 133     virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
 134
 135     virtual void delVirtPort(VirtualPort *vp) = 0;
 136
 137     virtual void connectMemPorts() = 0;
 138 #else
 139     virtual TranslatingPort *getMemPort() = 0;
 140
 141     virtual Process *getProcessPtr() = 0;
 142 #endif
 143
 144     virtual Status status() const = 0;
 145
 146     virtual void setStatus(Status new_status) = 0;
 147
 148     /// Set the status to Active.  Optional delay indicates number of
 149     /// cycles to wait before beginning execution.
 150     virtual void activate(int delay = 1) = 0;
 151
 152     /// Set the status to Suspended.
 153     virtual void suspend() = 0;
 154
 155     /// Set the status to Unallocated.
 156     virtual void deallocate(int delay = 0) = 0;
 157
 158     /// Set the status to Halted.
 159     virtual void halt() = 0;
 160
 161 #if FULL_SYSTEM
 162     virtual void dumpFuncProfile() = 0;
 163 #endif
 164
 165     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 166
 167     virtual void regStats(const std::string &name) = 0;
 168
 169     virtual void serialize(std::ostream &os) = 0;
 170     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 171
 172 #if FULL_SYSTEM
 173     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 174
 175     // Not necessarily the best location for these...
 176     // Having an extra function just to read these is obnoxious
 177     virtual Tick readLastActivate() = 0;
 178     virtual Tick readLastSuspend() = 0;
 179
 180     virtual void profileClear() = 0;
 181     virtual void profileSample() = 0;
 182 #endif
 183
 184     virtual int getThreadNum() = 0;
 185
 186     // Also somewhat obnoxious.  Really only used for the TLB fault.
 187     // However, may be quite useful in SPARC.
 188     virtual TheISA::MachInst getInst() = 0;
 189
 190     virtual void copyArchRegs(ThreadContext *tc) = 0;
 191
 192     virtual void clearArchRegs() = 0;
 193
 194     //
 195     // New accessors for new decoder.
 196     //
 197     virtual uint64_t readIntReg(int reg_idx) = 0;
 198
 199     virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
 200
 201     virtual FloatReg readFloatReg(int reg_idx) = 0;
 202
 203     virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
 204
 205     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 206
 207     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 208
 209     virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
 210
 211     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 212
 213     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 214
 215     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
 216
 217     virtual uint64_t readPC() = 0;
 218
 219     virtual void setPC(uint64_t val) = 0;
 220
 221     virtual uint64_t readNextPC() = 0;
 222
 223     virtual void setNextPC(uint64_t val) = 0;
 224
 225     virtual uint64_t readNextNPC() = 0;
 226
 227     virtual void setNextNPC(uint64_t val) = 0;
 228
 229     virtual MiscReg readMiscReg(int misc_reg) = 0;
 230
 231     virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
 232
 233     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 234
 235     virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
 236
 237     // Also not necessarily the best location for these two.  Hopefully will go
 238     // away once we decide upon where st cond failures goes.
 239     virtual unsigned readStCondFailures() = 0;
 240
 241     virtual void setStCondFailures(unsigned sc_failures) = 0;
 242
 243     // Only really makes sense for old CPU model.  Still could be useful though.
 244     virtual bool misspeculating() = 0;
 245
 246 #if !FULL_SYSTEM
 247     virtual IntReg getSyscallArg(int i) = 0;
 248
 249     // used to shift args for indirect syscall
 250     virtual void setSyscallArg(int i, IntReg val) = 0;
 251
 252     virtual void setSyscallReturn(SyscallReturn return_value) = 0;
 253
 254     // Same with st cond failures.
 255     virtual Counter readFuncExeInst() = 0;
 256
 257     // This function exits the thread context in the CPU and returns
 258     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 259     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 260     virtual int exit() { return 1; };
 261 #endif
 262
 263     virtual void changeRegFileContext(TheISA::RegContextParam param,
 264             TheISA::RegContextVal val) = 0;
 265 };
 266
 267 /**
 268  * ProxyThreadContext class that provides a way to implement a
 269  * ThreadContext without having to derive from it. ThreadContext is an
 270  * abstract class, so anything that derives from it and uses its
 271  * interface will pay the overhead of virtual function calls.  This
 272  * class is created to enable a user-defined Thread object to be used
 273  * wherever ThreadContexts are used, without paying the overhead of
 274  * virtual function calls when it is used by itself.  See
 275  * simple_thread.hh for an example of this.
 276  */
 277 template <class TC>
 278 class ProxyThreadContext : public ThreadContext
 279 {
 280   public:
 281     ProxyThreadContext(TC *actual_tc)
 282     { actualTC = actual_tc; }
 283
 284   private:
 285     TC *actualTC;
 286
 287   public:
 288
 289     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 290
 291     void setCpuId(int id) { actualTC->setCpuId(id); }
 292
 293     int readCpuId() { return actualTC->readCpuId(); }
 294
 295 #if FULL_SYSTEM
 296     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 297
 298     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 299
 300     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 301
 302     TheISA::Kernel::Statistics *getKernelStats()
 303     { return actualTC->getKernelStats(); }
 304
 305     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 306
 307     VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
 308
 309     void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
 310
 311     void connectMemPorts() { actualTC->connectMemPorts(); }
 312 #else
 313     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 314
 315     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 316 #endif
 317
 318     Status status() const { return actualTC->status(); }
 319
 320     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 321
 322     /// Set the status to Active.  Optional delay indicates number of
 323     /// cycles to wait before beginning execution.
 324     void activate(int delay = 1) { actualTC->activate(delay); }
 325
 326     /// Set the status to Suspended.
 327     void suspend() { actualTC->suspend(); }
 328
 329     /// Set the status to Unallocated.
 330     void deallocate(int delay = 0) { actualTC->deallocate(); }
 331
 332     /// Set the status to Halted.
 333     void halt() { actualTC->halt(); }
 334
 335 #if FULL_SYSTEM
 336     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 337 #endif
 338
 339     void takeOverFrom(ThreadContext *oldContext)
 340     { actualTC->takeOverFrom(oldContext); }
 341
 342     void regStats(const std::string &name) { actualTC->regStats(name); }
 343
 344     void serialize(std::ostream &os) { actualTC->serialize(os); }
 345     void unserialize(Checkpoint *cp, const std::string &section)
 346     { actualTC->unserialize(cp, section); }
 347
 348 #if FULL_SYSTEM
 349     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 350
 351     Tick readLastActivate() { return actualTC->readLastActivate(); }
 352     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 353
 354     void profileClear() { return actualTC->profileClear(); }
 355     void profileSample() { return actualTC->profileSample(); }
 356 #endif
 357
 358     int getThreadNum() { return actualTC->getThreadNum(); }
 359
 360     // @todo: Do I need this?
 361     MachInst getInst() { return actualTC->getInst(); }
 362
 363     // @todo: Do I need this?
 364     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 365
 366     void clearArchRegs() { actualTC->clearArchRegs(); }
 367
 368     //
 369     // New accessors for new decoder.
 370     //
 371     uint64_t readIntReg(int reg_idx)
 372     { return actualTC->readIntReg(reg_idx); }
 373
 374     FloatReg readFloatReg(int reg_idx, int width)
 375     { return actualTC->readFloatReg(reg_idx, width); }
 376
 377     FloatReg readFloatReg(int reg_idx)
 378     { return actualTC->readFloatReg(reg_idx); }
 379
 380     FloatRegBits readFloatRegBits(int reg_idx, int width)
 381     { return actualTC->readFloatRegBits(reg_idx, width); }
 382
 383     FloatRegBits readFloatRegBits(int reg_idx)
 384     { return actualTC->readFloatRegBits(reg_idx); }
 385
 386     void setIntReg(int reg_idx, uint64_t val)
 387     { actualTC->setIntReg(reg_idx, val); }
 388
 389     void setFloatReg(int reg_idx, FloatReg val, int width)
 390     { actualTC->setFloatReg(reg_idx, val, width); }
 391
 392     void setFloatReg(int reg_idx, FloatReg val)
 393     { actualTC->setFloatReg(reg_idx, val); }
 394
 395     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 396     { actualTC->setFloatRegBits(reg_idx, val, width); }
 397
 398     void setFloatRegBits(int reg_idx, FloatRegBits val)
 399     { actualTC->setFloatRegBits(reg_idx, val); }
 400
 401     uint64_t readPC() { return actualTC->readPC(); }
 402
 403     void setPC(uint64_t val) { actualTC->setPC(val); }
 404
 405     uint64_t readNextPC() { return actualTC->readNextPC(); }
 406
 407     void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
 408
 409     uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 410
 411     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 412
 413     MiscReg readMiscReg(int misc_reg)
 414     { return actualTC->readMiscReg(misc_reg); }
 415
 416     MiscReg readMiscRegWithEffect(int misc_reg)
 417     { return actualTC->readMiscRegWithEffect(misc_reg); }
 418
 419     void setMiscReg(int misc_reg, const MiscReg &val)
 420     { return actualTC->setMiscReg(misc_reg, val); }
 421
 422     void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 423     { return actualTC->setMiscRegWithEffect(misc_reg, val); }
 424
 425     unsigned readStCondFailures()
 426     { return actualTC->readStCondFailures(); }
 427
 428     void setStCondFailures(unsigned sc_failures)
 429     { actualTC->setStCondFailures(sc_failures); }
 430
 431     // @todo: Fix this!
 432     bool misspeculating() { return actualTC->misspeculating(); }
 433
 434 #if !FULL_SYSTEM
 435     IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
 436
 437     // used to shift args for indirect syscall
 438     void setSyscallArg(int i, IntReg val)
 439     { actualTC->setSyscallArg(i, val); }
 440
 441     void setSyscallReturn(SyscallReturn return_value)
 442     { actualTC->setSyscallReturn(return_value); }
 443
 444     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 445 #endif
 446
 447     void changeRegFileContext(TheISA::RegContextParam param,
 448             TheISA::RegContextVal val)
 449     {
 450         actualTC->changeRegFileContext(param, val);
 451     }
 452 };
 453
 454 #endif