src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016-2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_THREAD_CONTEXT_HH__
  45 #define __CPU_THREAD_CONTEXT_HH__
  46
  47 #include <iostream>
  48 #include <string>
  49
  50 #include "arch/registers.hh"
  51 #include "arch/types.hh"
  52 #include "base/types.hh"
  53 #include "config/the_isa.hh"
  54 #include "cpu/reg_class.hh"
  55
  56 // @todo: Figure out a more architecture independent way to obtain the ITB and
  57 // DTB pointers.
  58 namespace TheISA
  59 {
  60     class Decoder;
  61 }
  62 class BaseCPU;
  63 class BaseTLB;
  64 class CheckerCPU;
  65 class Checkpoint;
  66 class EndQuiesceEvent;
  67 class SETranslatingPortProxy;
  68 class FSTranslatingPortProxy;
  69 class PortProxy;
  70 class Process;
  71 class System;
  72 namespace TheISA {
  73     namespace Kernel {
  74         class Statistics;
  75     }
  76 }
  77
  78 /**
  79  * ThreadContext is the external interface to all thread state for
  80  * anything outside of the CPU. It provides all accessor methods to
  81  * state that might be needed by external objects, ranging from
  82  * register values to things such as kernel stats. It is an abstract
  83  * base class; the CPU can create its own ThreadContext by either
  84  * deriving from it, or using the templated ProxyThreadContext.
  85  *
  86  * The ThreadContext is slightly different than the ExecContext.  The
  87  * ThreadContext provides access to an individual thread's state; an
  88  * ExecContext provides ISA access to the CPU (meaning it is
  89  * implicitly multithreaded on SMT systems).  Additionally the
  90  * ThreadState is an abstract class that exactly defines the
  91  * interface; the ExecContext is a more implicit interface that must
  92  * be implemented so that the ISA can access whatever state it needs.
  93  */
  94 class ThreadContext
  95 {
  96   protected:
  97     typedef TheISA::MachInst MachInst;
  98     typedef TheISA::CCReg CCReg;
  99     using VecRegContainer = TheISA::VecRegContainer;
 100     using VecElem = TheISA::VecElem;
 101     using VecPredRegContainer = TheISA::VecPredRegContainer;
 102
 103   public:
 104
 105     enum Status
 106     {
 107         /// Running.  Instructions should be executed only when
 108         /// the context is in this state.
 109         Active,
 110
 111         /// Temporarily inactive.  Entered while waiting for
 112         /// synchronization, etc.
 113         Suspended,
 114
 115         /// Permanently shut down.  Entered when target executes
 116         /// m5exit pseudo-instruction.  When all contexts enter
 117         /// this state, the simulation will terminate.
 118         Halted
 119     };
 120
 121     virtual ~ThreadContext() { };
 122
 123     virtual BaseCPU *getCpuPtr() = 0;
 124
 125     virtual int cpuId() const = 0;
 126
 127     virtual uint32_t socketId() const = 0;
 128
 129     virtual int threadId() const = 0;
 130
 131     virtual void setThreadId(int id) = 0;
 132
 133     virtual int contextId() const = 0;
 134
 135     virtual void setContextId(int id) = 0;
 136
 137     virtual BaseTLB *getITBPtr() = 0;
 138
 139     virtual BaseTLB *getDTBPtr() = 0;
 140
 141     virtual CheckerCPU *getCheckerCpuPtr() = 0;
 142
 143     virtual TheISA::Decoder *getDecoderPtr() = 0;
 144
 145     virtual System *getSystemPtr() = 0;
 146
 147     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 148
 149     virtual PortProxy &getPhysProxy() = 0;
 150
 151     virtual FSTranslatingPortProxy &getVirtProxy() = 0;
 152
 153     /**
 154      * Initialise the physical and virtual port proxies and tie them to
 155      * the data port of the CPU.
 156      *
 157      * tc ThreadContext for the virtual-to-physical translation
 158      */
 159     virtual void initMemProxies(ThreadContext *tc) = 0;
 160
 161     virtual SETranslatingPortProxy &getMemProxy() = 0;
 162
 163     virtual Process *getProcessPtr() = 0;
 164
 165     virtual void setProcessPtr(Process *p) = 0;
 166
 167     virtual Status status() const = 0;
 168
 169     virtual void setStatus(Status new_status) = 0;
 170
 171     /// Set the status to Active.
 172     virtual void activate() = 0;
 173
 174     /// Set the status to Suspended.
 175     virtual void suspend() = 0;
 176
 177     /// Set the status to Halted.
 178     virtual void halt() = 0;
 179
 180     /// Quiesce thread context
 181     void quiesce();
 182
 183     /// Quiesce, suspend, and schedule activate at resume
 184     void quiesceTick(Tick resume);
 185
 186     virtual void dumpFuncProfile() = 0;
 187
 188     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 189
 190     virtual void regStats(const std::string &name) = 0;
 191
 192     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 193
 194     // Not necessarily the best location for these...
 195     // Having an extra function just to read these is obnoxious
 196     virtual Tick readLastActivate() = 0;
 197     virtual Tick readLastSuspend() = 0;
 198
 199     virtual void profileClear() = 0;
 200     virtual void profileSample() = 0;
 201
 202     virtual void copyArchRegs(ThreadContext *tc) = 0;
 203
 204     virtual void clearArchRegs() = 0;
 205
 206     //
 207     // New accessors for new decoder.
 208     //
 209     virtual RegVal readIntReg(int reg_idx) = 0;
 210
 211     virtual RegVal readFloatRegBits(int reg_idx) = 0;
 212
 213     virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
 214     virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
 215
 216     /** Vector Register Lane Interfaces. */
 217     /** @{ */
 218     /** Reads source vector 8bit operand. */
 219     virtual ConstVecLane8
 220     readVec8BitLaneReg(const RegId& reg) const = 0;
 221
 222     /** Reads source vector 16bit operand. */
 223     virtual ConstVecLane16
 224     readVec16BitLaneReg(const RegId& reg) const = 0;
 225
 226     /** Reads source vector 32bit operand. */
 227     virtual ConstVecLane32
 228     readVec32BitLaneReg(const RegId& reg) const = 0;
 229
 230     /** Reads source vector 64bit operand. */
 231     virtual ConstVecLane64
 232     readVec64BitLaneReg(const RegId& reg) const = 0;
 233
 234     /** Write a lane of the destination vector register. */
 235     virtual void setVecLane(const RegId& reg,
 236             const LaneData<LaneSize::Byte>& val) = 0;
 237     virtual void setVecLane(const RegId& reg,
 238             const LaneData<LaneSize::TwoByte>& val) = 0;
 239     virtual void setVecLane(const RegId& reg,
 240             const LaneData<LaneSize::FourByte>& val) = 0;
 241     virtual void setVecLane(const RegId& reg,
 242             const LaneData<LaneSize::EightByte>& val) = 0;
 243     /** @} */
 244
 245     virtual const VecElem& readVecElem(const RegId& reg) const = 0;
 246
 247     virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
 248         const = 0;
 249     virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
 250
 251     virtual CCReg readCCReg(int reg_idx) = 0;
 252
 253     virtual void setIntReg(int reg_idx, RegVal val) = 0;
 254
 255     virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;
 256
 257     virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
 258
 259     virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
 260
 261     virtual void setVecPredReg(const RegId& reg,
 262                                const VecPredRegContainer& val) = 0;
 263
 264     virtual void setCCReg(int reg_idx, CCReg val) = 0;
 265
 266     virtual TheISA::PCState pcState() = 0;
 267
 268     virtual void pcState(const TheISA::PCState &val) = 0;
 269
 270     void
 271     setNPC(Addr val)
 272     {
 273         TheISA::PCState pc_state = pcState();
 274         pc_state.setNPC(val);
 275         pcState(pc_state);
 276     }
 277
 278     virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 279
 280     virtual Addr instAddr() = 0;
 281
 282     virtual Addr nextInstAddr() = 0;
 283
 284     virtual MicroPC microPC() = 0;
 285
 286     virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;
 287
 288     virtual RegVal readMiscReg(int misc_reg) = 0;
 289
 290     virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
 291
 292     virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 293
 294     virtual RegId flattenRegId(const RegId& regId) const = 0;
 295
 296     virtual RegVal
 297     readRegOtherThread(const RegId& misc_reg, ThreadID tid)
 298     {
 299         return 0;
 300     }
 301
 302     virtual void
 303     setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
 304     {
 305     }
 306
 307     // Also not necessarily the best location for these two.  Hopefully will go
 308     // away once we decide upon where st cond failures goes.
 309     virtual unsigned readStCondFailures() = 0;
 310
 311     virtual void setStCondFailures(unsigned sc_failures) = 0;
 312
 313     // Same with st cond failures.
 314     virtual Counter readFuncExeInst() = 0;
 315
 316     virtual void syscall(int64_t callnum, Fault *fault) = 0;
 317
 318     // This function exits the thread context in the CPU and returns
 319     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 320     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 321     virtual int exit() { return 1; };
 322
 323     /** function to compare two thread contexts (for debugging) */
 324     static void compare(ThreadContext *one, ThreadContext *two);
 325
 326     /** @{ */
 327     /**
 328      * Flat register interfaces
 329      *
 330      * Some architectures have different registers visible in
 331      * different modes. Such architectures "flatten" a register (see
 332      * flattenRegId()) to map it into the
 333      * gem5 register file. This interface provides a flat interface to
 334      * the underlying register file, which allows for example
 335      * serialization code to access all registers.
 336      */
 337
 338     virtual RegVal readIntRegFlat(int idx) = 0;
 339     virtual void setIntRegFlat(int idx, RegVal val) = 0;
 340
 341     virtual RegVal readFloatRegBitsFlat(int idx) = 0;
 342     virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0;
 343
 344     virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
 345     virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
 346     virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
 347
 348     virtual const VecElem& readVecElemFlat(const RegIndex& idx,
 349                                            const ElemIndex& elemIdx) const = 0;
 350     virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
 351                                 const VecElem& val) = 0;
 352
 353     virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0;
 354     virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0;
 355     virtual void setVecPredRegFlat(int idx,
 356                                    const VecPredRegContainer& val) = 0;
 357
 358     virtual CCReg readCCRegFlat(int idx) = 0;
 359     virtual void setCCRegFlat(int idx, CCReg val) = 0;
 360     /** @} */
 361
 362 };
 363
 364 /**
 365  * ProxyThreadContext class that provides a way to implement a
 366  * ThreadContext without having to derive from it. ThreadContext is an
 367  * abstract class, so anything that derives from it and uses its
 368  * interface will pay the overhead of virtual function calls.  This
 369  * class is created to enable a user-defined Thread object to be used
 370  * wherever ThreadContexts are used, without paying the overhead of
 371  * virtual function calls when it is used by itself.  See
 372  * simple_thread.hh for an example of this.
 373  */
 374 template <class TC>
 375 class ProxyThreadContext : public ThreadContext
 376 {
 377   public:
 378     ProxyThreadContext(TC *actual_tc)
 379     { actualTC = actual_tc; }
 380
 381   private:
 382     TC *actualTC;
 383
 384   public:
 385
 386     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 387
 388     int cpuId() const { return actualTC->cpuId(); }
 389
 390     uint32_t socketId() const { return actualTC->socketId(); }
 391
 392     int threadId() const { return actualTC->threadId(); }
 393
 394     void setThreadId(int id) { actualTC->setThreadId(id); }
 395
 396     int contextId() const { return actualTC->contextId(); }
 397
 398     void setContextId(int id) { actualTC->setContextId(id); }
 399
 400     BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
 401
 402     BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 403
 404     CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
 405
 406     TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 407
 408     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 409
 410     TheISA::Kernel::Statistics *getKernelStats()
 411     { return actualTC->getKernelStats(); }
 412
 413     PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
 414
 415     FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
 416
 417     void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
 418
 419     SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
 420
 421     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 422
 423     void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
 424
 425     Status status() const { return actualTC->status(); }
 426
 427     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 428
 429     /// Set the status to Active.
 430     void activate() { actualTC->activate(); }
 431
 432     /// Set the status to Suspended.
 433     void suspend() { actualTC->suspend(); }
 434
 435     /// Set the status to Halted.
 436     void halt() { actualTC->halt(); }
 437
 438     /// Quiesce thread context
 439     void quiesce() { actualTC->quiesce(); }
 440
 441     /// Quiesce, suspend, and schedule activate at resume
 442     void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
 443
 444     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 445
 446     void takeOverFrom(ThreadContext *oldContext)
 447     { actualTC->takeOverFrom(oldContext); }
 448
 449     void regStats(const std::string &name) { actualTC->regStats(name); }
 450
 451     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 452
 453     Tick readLastActivate() { return actualTC->readLastActivate(); }
 454     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 455
 456     void profileClear() { return actualTC->profileClear(); }
 457     void profileSample() { return actualTC->profileSample(); }
 458
 459     // @todo: Do I need this?
 460     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 461
 462     void clearArchRegs() { actualTC->clearArchRegs(); }
 463
 464     //
 465     // New accessors for new decoder.
 466     //
 467     RegVal readIntReg(int reg_idx)
 468     { return actualTC->readIntReg(reg_idx); }
 469
 470     RegVal readFloatRegBits(int reg_idx)
 471     { return actualTC->readFloatRegBits(reg_idx); }
 472
 473     const VecRegContainer& readVecReg(const RegId& reg) const
 474     { return actualTC->readVecReg(reg); }
 475
 476     VecRegContainer& getWritableVecReg(const RegId& reg)
 477     { return actualTC->getWritableVecReg(reg); }
 478
 479     /** Vector Register Lane Interfaces. */
 480     /** @{ */
 481     /** Reads source vector 8bit operand. */
 482     ConstVecLane8
 483     readVec8BitLaneReg(const RegId& reg) const
 484     { return actualTC->readVec8BitLaneReg(reg); }
 485
 486     /** Reads source vector 16bit operand. */
 487     ConstVecLane16
 488     readVec16BitLaneReg(const RegId& reg) const
 489     { return actualTC->readVec16BitLaneReg(reg); }
 490
 491     /** Reads source vector 32bit operand. */
 492     ConstVecLane32
 493     readVec32BitLaneReg(const RegId& reg) const
 494     { return actualTC->readVec32BitLaneReg(reg); }
 495
 496     /** Reads source vector 64bit operand. */
 497     ConstVecLane64
 498     readVec64BitLaneReg(const RegId& reg) const
 499     { return actualTC->readVec64BitLaneReg(reg); }
 500
 501     /** Write a lane of the destination vector register. */
 502     virtual void setVecLane(const RegId& reg,
 503             const LaneData<LaneSize::Byte>& val)
 504     { return actualTC->setVecLane(reg, val); }
 505     virtual void setVecLane(const RegId& reg,
 506             const LaneData<LaneSize::TwoByte>& val)
 507     { return actualTC->setVecLane(reg, val); }
 508     virtual void setVecLane(const RegId& reg,
 509             const LaneData<LaneSize::FourByte>& val)
 510     { return actualTC->setVecLane(reg, val); }
 511     virtual void setVecLane(const RegId& reg,
 512             const LaneData<LaneSize::EightByte>& val)
 513     { return actualTC->setVecLane(reg, val); }
 514     /** @} */
 515
 516     const VecElem& readVecElem(const RegId& reg) const
 517     { return actualTC->readVecElem(reg); }
 518
 519     const VecPredRegContainer& readVecPredReg(const RegId& reg) const
 520     { return actualTC->readVecPredReg(reg); }
 521
 522     VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
 523     { return actualTC->getWritableVecPredReg(reg); }
 524
 525     CCReg readCCReg(int reg_idx)
 526     { return actualTC->readCCReg(reg_idx); }
 527
 528     void setIntReg(int reg_idx, RegVal val)
 529     { actualTC->setIntReg(reg_idx, val); }
 530
 531     void setFloatRegBits(int reg_idx, RegVal val)
 532     { actualTC->setFloatRegBits(reg_idx, val); }
 533
 534     void setVecReg(const RegId& reg, const VecRegContainer& val)
 535     { actualTC->setVecReg(reg, val); }
 536
 537     void setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
 538     { actualTC->setVecPredReg(reg, val); }
 539
 540     void setVecElem(const RegId& reg, const VecElem& val)
 541     { actualTC->setVecElem(reg, val); }
 542
 543     void setCCReg(int reg_idx, CCReg val)
 544     { actualTC->setCCReg(reg_idx, val); }
 545
 546     TheISA::PCState pcState() { return actualTC->pcState(); }
 547
 548     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 549
 550     void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
 551
 552     Addr instAddr() { return actualTC->instAddr(); }
 553     Addr nextInstAddr() { return actualTC->nextInstAddr(); }
 554     MicroPC microPC() { return actualTC->microPC(); }
 555
 556     bool readPredicate() { return actualTC->readPredicate(); }
 557
 558     void setPredicate(bool val)
 559     { actualTC->setPredicate(val); }
 560
 561     RegVal readMiscRegNoEffect(int misc_reg) const
 562     { return actualTC->readMiscRegNoEffect(misc_reg); }
 563
 564     RegVal readMiscReg(int misc_reg)
 565     { return actualTC->readMiscReg(misc_reg); }
 566
 567     void setMiscRegNoEffect(int misc_reg, RegVal val)
 568     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 569
 570     void setMiscReg(int misc_reg, RegVal val)
 571     { return actualTC->setMiscReg(misc_reg, val); }
 572
 573     RegId flattenRegId(const RegId& regId) const
 574     { return actualTC->flattenRegId(regId); }
 575
 576     unsigned readStCondFailures()
 577     { return actualTC->readStCondFailures(); }
 578
 579     void setStCondFailures(unsigned sc_failures)
 580     { actualTC->setStCondFailures(sc_failures); }
 581
 582     void syscall(int64_t callnum, Fault *fault)
 583     { actualTC->syscall(callnum, fault); }
 584
 585     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 586
 587     RegVal readIntRegFlat(int idx)
 588     { return actualTC->readIntRegFlat(idx); }
 589
 590     void setIntRegFlat(int idx, RegVal val)
 591     { actualTC->setIntRegFlat(idx, val); }
 592
 593     RegVal readFloatRegBitsFlat(int idx)
 594     { return actualTC->readFloatRegBitsFlat(idx); }
 595
 596     void setFloatRegBitsFlat(int idx, RegVal val)
 597     { actualTC->setFloatRegBitsFlat(idx, val); }
 598
 599     const VecRegContainer& readVecRegFlat(int id) const
 600     { return actualTC->readVecRegFlat(id); }
 601
 602     VecRegContainer& getWritableVecRegFlat(int id)
 603     { return actualTC->getWritableVecRegFlat(id); }
 604
 605     void setVecRegFlat(int idx, const VecRegContainer& val)
 606     { actualTC->setVecRegFlat(idx, val); }
 607
 608     const VecElem& readVecElemFlat(const RegIndex& id,
 609                                    const ElemIndex& elemIndex) const
 610     { return actualTC->readVecElemFlat(id, elemIndex); }
 611
 612     void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
 613                         const VecElem& val)
 614     { actualTC->setVecElemFlat(id, elemIndex, val); }
 615
 616     const VecPredRegContainer& readVecPredRegFlat(int id) const
 617     { return actualTC->readVecPredRegFlat(id); }
 618
 619     VecPredRegContainer& getWritableVecPredRegFlat(int id)
 620     { return actualTC->getWritableVecPredRegFlat(id); }
 621
 622     void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
 623     { actualTC->setVecPredRegFlat(idx, val); }
 624
 625     CCReg readCCRegFlat(int idx)
 626     { return actualTC->readCCRegFlat(idx); }
 627
 628     void setCCRegFlat(int idx, CCReg val)
 629     { actualTC->setCCRegFlat(idx, val); }
 630 };
 631
 632 /** @{ */
 633 /**
 634  * Thread context serialization helpers
 635  *
 636  * These helper functions provide a way to the data in a
 637  * ThreadContext. They are provided as separate helper function since
 638  * implementing them as members of the ThreadContext interface would
 639  * be confusing when the ThreadContext is exported via a proxy.
 640  */
 641
 642 void serialize(ThreadContext &tc, CheckpointOut &cp);
 643 void unserialize(ThreadContext &tc, CheckpointIn &cp);
 644
 645 /** @} */
 646
 647
 648 /**
 649  * Copy state between thread contexts in preparation for CPU handover.
 650  *
 651  * @note This method modifies the old thread contexts as well as the
 652  * new thread context. The old thread context will have its quiesce
 653  * event descheduled if it is scheduled and its status set to halted.
 654  *
 655  * @param new_tc Destination ThreadContext.
 656  * @param old_tc Source ThreadContext.
 657  */
 658 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
 659
 660 #endif