src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include "arch/regfile.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "mem/request.hh"
  38 #include "sim/faults.hh"
  39 #include "sim/host.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/byteswap.hh"
  42
  43 // @todo: Figure out a more architecture independent way to obtain the ITB and
  44 // DTB pointers.
  45 namespace TheISA
  46 {
  47     class DTB;
  48     class ITB;
  49 }
  50 class BaseCPU;
  51 class EndQuiesceEvent;
  52 class Event;
  53 class TranslatingPort;
  54 class FunctionalPort;
  55 class VirtualPort;
  56 class Process;
  57 class System;
  58 namespace TheISA {
  59     namespace Kernel {
  60         class Statistics;
  61     };
  62 };
  63
  64 /**
  65  * ThreadContext is the external interface to all thread state for
  66  * anything outside of the CPU. It provides all accessor methods to
  67  * state that might be needed by external objects, ranging from
  68  * register values to things such as kernel stats. It is an abstract
  69  * base class; the CPU can create its own ThreadContext by either
  70  * deriving from it, or using the templated ProxyThreadContext.
  71  *
  72  * The ThreadContext is slightly different than the ExecContext.  The
  73  * ThreadContext provides access to an individual thread's state; an
  74  * ExecContext provides ISA access to the CPU (meaning it is
  75  * implicitly multithreaded on SMT systems).  Additionally the
  76  * ThreadState is an abstract class that exactly defines the
  77  * interface; the ExecContext is a more implicit interface that must
  78  * be implemented so that the ISA can access whatever state it needs.
  79  */
  80 class ThreadContext
  81 {
  82   protected:
  83     typedef TheISA::RegFile RegFile;
  84     typedef TheISA::MachInst MachInst;
  85     typedef TheISA::IntReg IntReg;
  86     typedef TheISA::FloatReg FloatReg;
  87     typedef TheISA::FloatRegBits FloatRegBits;
  88     typedef TheISA::MiscRegFile MiscRegFile;
  89     typedef TheISA::MiscReg MiscReg;
  90   public:
  91     enum Status
  92     {
  93         /// Initialized but not running yet.  All CPUs start in
  94         /// this state, but most transition to Active on cycle 1.
  95         /// In MP or SMT systems, non-primary contexts will stay
  96         /// in this state until a thread is assigned to them.
  97         Unallocated,
  98
  99         /// Running.  Instructions should be executed only when
 100         /// the context is in this state.
 101         Active,
 102
 103         /// Temporarily inactive.  Entered while waiting for
 104         /// synchronization, etc.
 105         Suspended,
 106
 107         /// Permanently shut down.  Entered when target executes
 108         /// m5exit pseudo-instruction.  When all contexts enter
 109         /// this state, the simulation will terminate.
 110         Halted
 111     };
 112
 113     virtual ~ThreadContext() { };
 114
 115     virtual BaseCPU *getCpuPtr() = 0;
 116
 117     virtual int cpuId() = 0;
 118
 119     virtual int threadId() = 0;
 120
 121     virtual void setThreadId(int id) = 0;
 122
 123     virtual int contextId() = 0;
 124
 125     virtual void setContextId(int id) = 0;
 126
 127     virtual TheISA::ITB *getITBPtr() = 0;
 128
 129     virtual TheISA::DTB *getDTBPtr() = 0;
 130
 131     virtual System *getSystemPtr() = 0;
 132
 133 #if FULL_SYSTEM
 134     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 135
 136     virtual FunctionalPort *getPhysPort() = 0;
 137
 138     virtual VirtualPort *getVirtPort() = 0;
 139
 140     virtual void connectMemPorts(ThreadContext *tc) = 0;
 141 #else
 142     virtual TranslatingPort *getMemPort() = 0;
 143
 144     virtual Process *getProcessPtr() = 0;
 145 #endif
 146
 147     virtual Status status() const = 0;
 148
 149     virtual void setStatus(Status new_status) = 0;
 150
 151     /// Set the status to Active.  Optional delay indicates number of
 152     /// cycles to wait before beginning execution.
 153     virtual void activate(int delay = 1) = 0;
 154
 155     /// Set the status to Suspended.
 156     virtual void suspend(int delay = 0) = 0;
 157
 158     /// Set the status to Unallocated.
 159     virtual void deallocate(int delay = 0) = 0;
 160
 161     /// Set the status to Halted.
 162     virtual void halt(int delay = 0) = 0;
 163
 164 #if FULL_SYSTEM
 165     virtual void dumpFuncProfile() = 0;
 166 #endif
 167
 168     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 169
 170     virtual void regStats(const std::string &name) = 0;
 171
 172     virtual void serialize(std::ostream &os) = 0;
 173     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 174
 175 #if FULL_SYSTEM
 176     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 177
 178     // Not necessarily the best location for these...
 179     // Having an extra function just to read these is obnoxious
 180     virtual Tick readLastActivate() = 0;
 181     virtual Tick readLastSuspend() = 0;
 182
 183     virtual void profileClear() = 0;
 184     virtual void profileSample() = 0;
 185 #endif
 186
 187     // Also somewhat obnoxious.  Really only used for the TLB fault.
 188     // However, may be quite useful in SPARC.
 189     virtual TheISA::MachInst getInst() = 0;
 190
 191     virtual void copyArchRegs(ThreadContext *tc) = 0;
 192
 193     virtual void clearArchRegs() = 0;
 194
 195     //
 196     // New accessors for new decoder.
 197     //
 198     virtual uint64_t readIntReg(int reg_idx) = 0;
 199
 200     virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
 201
 202     virtual FloatReg readFloatReg(int reg_idx) = 0;
 203
 204     virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
 205
 206     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 207
 208     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 209
 210     virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
 211
 212     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 213
 214     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 215
 216     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
 217
 218     virtual uint64_t readPC() = 0;
 219
 220     virtual void setPC(uint64_t val) = 0;
 221
 222     virtual uint64_t readNextPC() = 0;
 223
 224     virtual void setNextPC(uint64_t val) = 0;
 225
 226     virtual uint64_t readNextNPC() = 0;
 227
 228     virtual void setNextNPC(uint64_t val) = 0;
 229
 230     virtual uint64_t readMicroPC() = 0;
 231
 232     virtual void setMicroPC(uint64_t val) = 0;
 233
 234     virtual uint64_t readNextMicroPC() = 0;
 235
 236     virtual void setNextMicroPC(uint64_t val) = 0;
 237
 238     virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 239
 240     virtual MiscReg readMiscReg(int misc_reg) = 0;
 241
 242     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 243
 244     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 245
 246     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
 247
 248     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
 249
 250     // Also not necessarily the best location for these two.  Hopefully will go
 251     // away once we decide upon where st cond failures goes.
 252     virtual unsigned readStCondFailures() = 0;
 253
 254     virtual void setStCondFailures(unsigned sc_failures) = 0;
 255
 256     // Only really makes sense for old CPU model.  Still could be useful though.
 257     virtual bool misspeculating() = 0;
 258
 259 #if !FULL_SYSTEM
 260     // Same with st cond failures.
 261     virtual Counter readFuncExeInst() = 0;
 262
 263     virtual void syscall(int64_t callnum) = 0;
 264
 265     // This function exits the thread context in the CPU and returns
 266     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 267     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 268     virtual int exit() { return 1; };
 269 #endif
 270
 271     /** function to compare two thread contexts (for debugging) */
 272     static void compare(ThreadContext *one, ThreadContext *two);
 273 };
 274
 275 /**
 276  * ProxyThreadContext class that provides a way to implement a
 277  * ThreadContext without having to derive from it. ThreadContext is an
 278  * abstract class, so anything that derives from it and uses its
 279  * interface will pay the overhead of virtual function calls.  This
 280  * class is created to enable a user-defined Thread object to be used
 281  * wherever ThreadContexts are used, without paying the overhead of
 282  * virtual function calls when it is used by itself.  See
 283  * simple_thread.hh for an example of this.
 284  */
 285 template <class TC>
 286 class ProxyThreadContext : public ThreadContext
 287 {
 288   public:
 289     ProxyThreadContext(TC *actual_tc)
 290     { actualTC = actual_tc; }
 291
 292   private:
 293     TC *actualTC;
 294
 295   public:
 296
 297     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 298
 299     int cpuId() { return actualTC->cpuId(); }
 300
 301     int threadId() { return actualTC->threadId(); }
 302
 303     void setThreadId(int id) { return actualTC->setThreadId(id); }
 304
 305     int contextId() { return actualTC->contextId(); }
 306
 307     void setContextId(int id) { actualTC->setContextId(id); }
 308
 309     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 310
 311     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 312
 313     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 314
 315 #if FULL_SYSTEM
 316     TheISA::Kernel::Statistics *getKernelStats()
 317     { return actualTC->getKernelStats(); }
 318
 319     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 320
 321     VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
 322
 323     void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 324 #else
 325     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 326
 327     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 328 #endif
 329
 330     Status status() const { return actualTC->status(); }
 331
 332     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 333
 334     /// Set the status to Active.  Optional delay indicates number of
 335     /// cycles to wait before beginning execution.
 336     void activate(int delay = 1) { actualTC->activate(delay); }
 337
 338     /// Set the status to Suspended.
 339     void suspend(int delay = 0) { actualTC->suspend(); }
 340
 341     /// Set the status to Unallocated.
 342     void deallocate(int delay = 0) { actualTC->deallocate(); }
 343
 344     /// Set the status to Halted.
 345     void halt(int delay = 0) { actualTC->halt(); }
 346
 347 #if FULL_SYSTEM
 348     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 349 #endif
 350
 351     void takeOverFrom(ThreadContext *oldContext)
 352     { actualTC->takeOverFrom(oldContext); }
 353
 354     void regStats(const std::string &name) { actualTC->regStats(name); }
 355
 356     void serialize(std::ostream &os) { actualTC->serialize(os); }
 357     void unserialize(Checkpoint *cp, const std::string &section)
 358     { actualTC->unserialize(cp, section); }
 359
 360 #if FULL_SYSTEM
 361     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 362
 363     Tick readLastActivate() { return actualTC->readLastActivate(); }
 364     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 365
 366     void profileClear() { return actualTC->profileClear(); }
 367     void profileSample() { return actualTC->profileSample(); }
 368 #endif
 369     // @todo: Do I need this?
 370     MachInst getInst() { return actualTC->getInst(); }
 371
 372     // @todo: Do I need this?
 373     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 374
 375     void clearArchRegs() { actualTC->clearArchRegs(); }
 376
 377     //
 378     // New accessors for new decoder.
 379     //
 380     uint64_t readIntReg(int reg_idx)
 381     { return actualTC->readIntReg(reg_idx); }
 382
 383     FloatReg readFloatReg(int reg_idx, int width)
 384     { return actualTC->readFloatReg(reg_idx, width); }
 385
 386     FloatReg readFloatReg(int reg_idx)
 387     { return actualTC->readFloatReg(reg_idx); }
 388
 389     FloatRegBits readFloatRegBits(int reg_idx, int width)
 390     { return actualTC->readFloatRegBits(reg_idx, width); }
 391
 392     FloatRegBits readFloatRegBits(int reg_idx)
 393     { return actualTC->readFloatRegBits(reg_idx); }
 394
 395     void setIntReg(int reg_idx, uint64_t val)
 396     { actualTC->setIntReg(reg_idx, val); }
 397
 398     void setFloatReg(int reg_idx, FloatReg val, int width)
 399     { actualTC->setFloatReg(reg_idx, val, width); }
 400
 401     void setFloatReg(int reg_idx, FloatReg val)
 402     { actualTC->setFloatReg(reg_idx, val); }
 403
 404     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 405     { actualTC->setFloatRegBits(reg_idx, val, width); }
 406
 407     void setFloatRegBits(int reg_idx, FloatRegBits val)
 408     { actualTC->setFloatRegBits(reg_idx, val); }
 409
 410     uint64_t readPC() { return actualTC->readPC(); }
 411
 412     void setPC(uint64_t val) { actualTC->setPC(val); }
 413
 414     uint64_t readNextPC() { return actualTC->readNextPC(); }
 415
 416     void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
 417
 418     uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 419
 420     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 421
 422     uint64_t readMicroPC() { return actualTC->readMicroPC(); }
 423
 424     void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
 425
 426     uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
 427
 428     void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
 429
 430     MiscReg readMiscRegNoEffect(int misc_reg)
 431     { return actualTC->readMiscRegNoEffect(misc_reg); }
 432
 433     MiscReg readMiscReg(int misc_reg)
 434     { return actualTC->readMiscReg(misc_reg); }
 435
 436     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 437     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 438
 439     void setMiscReg(int misc_reg, const MiscReg &val)
 440     { return actualTC->setMiscReg(misc_reg, val); }
 441
 442     unsigned readStCondFailures()
 443     { return actualTC->readStCondFailures(); }
 444
 445     void setStCondFailures(unsigned sc_failures)
 446     { actualTC->setStCondFailures(sc_failures); }
 447
 448     // @todo: Fix this!
 449     bool misspeculating() { return actualTC->misspeculating(); }
 450
 451 #if !FULL_SYSTEM
 452     void syscall(int64_t callnum)
 453     { actualTC->syscall(callnum); }
 454
 455     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 456 #endif
 457 };
 458
 459 #endif