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31 #ifndef __CPU_THREAD_CONTEXT_HH__
32 #define __CPU_THREAD_CONTEXT_HH__
34 #include "arch/types.hh"
35 #include "arch/regfile.hh"
36 #include "arch/syscallreturn.hh"
37 #include "config/full_system.hh"
38 #include "mem/request.hh"
39 #include "sim/faults.hh"
40 #include "sim/host.hh"
41 #include "sim/serialize.hh"
42 #include "sim/byteswap.hh"
44 // @todo: Figure out a more architecture independent way to obtain the ITB and
49 class EndQuiesceEvent;
51 class TranslatingPort;
61 * ThreadContext is the external interface to all thread state for
62 * anything outside of the CPU. It provides all accessor methods to
63 * state that might be needed by external objects, ranging from
64 * register values to things such as kernel stats. It is an abstract
65 * base class; the CPU can create its own ThreadContext by either
66 * deriving from it, or using the templated ProxyThreadContext.
68 * The ThreadContext is slightly different than the ExecContext. The
69 * ThreadContext provides access to an individual thread's state; an
70 * ExecContext provides ISA access to the CPU (meaning it is
71 * implicitly multithreaded on SMT systems). Additionally the
72 * ThreadState is an abstract class that exactly defines the
73 * interface; the ExecContext is a more implicit interface that must
74 * be implemented so that the ISA can access whatever state it needs.
79 typedef TheISA::RegFile RegFile;
80 typedef TheISA::MachInst MachInst;
81 typedef TheISA::IntReg IntReg;
82 typedef TheISA::FloatReg FloatReg;
83 typedef TheISA::FloatRegBits FloatRegBits;
84 typedef TheISA::MiscRegFile MiscRegFile;
85 typedef TheISA::MiscReg MiscReg;
89 /// Initialized but not running yet. All CPUs start in
90 /// this state, but most transition to Active on cycle 1.
91 /// In MP or SMT systems, non-primary contexts will stay
92 /// in this state until a thread is assigned to them.
95 /// Running. Instructions should be executed only when
96 /// the context is in this state.
99 /// Temporarily inactive. Entered while waiting for
100 /// synchronization, etc.
103 /// Permanently shut down. Entered when target executes
104 /// m5exit pseudo-instruction. When all contexts enter
105 /// this state, the simulation will terminate.
109 virtual ~ThreadContext() { };
111 virtual BaseCPU *getCpuPtr() = 0;
113 virtual void setCpuId(int id) = 0;
115 virtual int readCpuId() = 0;
118 virtual System *getSystemPtr() = 0;
120 virtual AlphaITB *getITBPtr() = 0;
122 virtual AlphaDTB * getDTBPtr() = 0;
124 virtual Kernel::Statistics *getKernelStats() = 0;
126 virtual FunctionalPort *getPhysPort() = 0;
128 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
130 virtual void delVirtPort(VirtualPort *vp) = 0;
132 virtual TranslatingPort *getMemPort() = 0;
134 virtual Process *getProcessPtr() = 0;
137 virtual Status status() const = 0;
139 virtual void setStatus(Status new_status) = 0;
141 /// Set the status to Active. Optional delay indicates number of
142 /// cycles to wait before beginning execution.
143 virtual void activate(int delay = 1) = 0;
145 /// Set the status to Suspended.
146 virtual void suspend() = 0;
148 /// Set the status to Unallocated.
149 virtual void deallocate(int delay = 0) = 0;
151 /// Set the status to Halted.
152 virtual void halt() = 0;
155 virtual void dumpFuncProfile() = 0;
158 virtual void takeOverFrom(ThreadContext *old_context) = 0;
160 virtual void regStats(const std::string &name) = 0;
162 virtual void serialize(std::ostream &os) = 0;
163 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
166 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
168 // Not necessarily the best location for these...
169 // Having an extra function just to read these is obnoxious
170 virtual Tick readLastActivate() = 0;
171 virtual Tick readLastSuspend() = 0;
173 virtual void profileClear() = 0;
174 virtual void profileSample() = 0;
177 virtual int getThreadNum() = 0;
179 // Also somewhat obnoxious. Really only used for the TLB fault.
180 // However, may be quite useful in SPARC.
181 virtual TheISA::MachInst getInst() = 0;
183 virtual void copyArchRegs(ThreadContext *tc) = 0;
185 virtual void clearArchRegs() = 0;
188 // New accessors for new decoder.
190 virtual uint64_t readIntReg(int reg_idx) = 0;
192 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
194 virtual FloatReg readFloatReg(int reg_idx) = 0;
196 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
198 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
200 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
202 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
204 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
206 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
208 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
210 virtual uint64_t readPC() = 0;
212 virtual void setPC(uint64_t val) = 0;
214 virtual uint64_t readNextPC() = 0;
216 virtual void setNextPC(uint64_t val) = 0;
218 virtual uint64_t readNextNPC() = 0;
220 virtual void setNextNPC(uint64_t val) = 0;
222 virtual MiscReg readMiscReg(int misc_reg) = 0;
224 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
226 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
228 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
230 // Also not necessarily the best location for these two. Hopefully will go
231 // away once we decide upon where st cond failures goes.
232 virtual unsigned readStCondFailures() = 0;
234 virtual void setStCondFailures(unsigned sc_failures) = 0;
237 virtual bool inPalMode() = 0;
240 // Only really makes sense for old CPU model. Still could be useful though.
241 virtual bool misspeculating() = 0;
244 virtual IntReg getSyscallArg(int i) = 0;
246 // used to shift args for indirect syscall
247 virtual void setSyscallArg(int i, IntReg val) = 0;
249 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
251 // Same with st cond failures.
252 virtual Counter readFuncExeInst() = 0;
254 // This function exits the thread context in the CPU and returns
255 // 1 if the CPU has no more active threads (meaning it's OK to exit);
256 // Used in syscall-emulation mode when a thread calls the exit syscall.
257 virtual int exit() { return 1; };
260 virtual void changeRegFileContext(TheISA::RegContextParam param,
261 TheISA::RegContextVal val) = 0;
265 * ProxyThreadContext class that provides a way to implement a
266 * ThreadContext without having to derive from it. ThreadContext is an
267 * abstract class, so anything that derives from it and uses its
268 * interface will pay the overhead of virtual function calls. This
269 * class is created to enable a user-defined Thread object to be used
270 * wherever ThreadContexts are used, without paying the overhead of
271 * virtual function calls when it is used by itself. See
272 * simple_thread.hh for an example of this.
275 class ProxyThreadContext : public ThreadContext
278 ProxyThreadContext(TC *actual_tc)
279 { actualTC = actual_tc; }
286 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
288 void setCpuId(int id) { actualTC->setCpuId(id); }
290 int readCpuId() { return actualTC->readCpuId(); }
293 System *getSystemPtr() { return actualTC->getSystemPtr(); }
295 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
297 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
299 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
301 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
303 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
305 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
307 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
309 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
312 Status status() const { return actualTC->status(); }
314 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
316 /// Set the status to Active. Optional delay indicates number of
317 /// cycles to wait before beginning execution.
318 void activate(int delay = 1) { actualTC->activate(delay); }
320 /// Set the status to Suspended.
321 void suspend() { actualTC->suspend(); }
323 /// Set the status to Unallocated.
324 void deallocate(int delay = 0) { actualTC->deallocate(); }
326 /// Set the status to Halted.
327 void halt() { actualTC->halt(); }
330 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
333 void takeOverFrom(ThreadContext *oldContext)
334 { actualTC->takeOverFrom(oldContext); }
336 void regStats(const std::string &name) { actualTC->regStats(name); }
338 void serialize(std::ostream &os) { actualTC->serialize(os); }
339 void unserialize(Checkpoint *cp, const std::string §ion)
340 { actualTC->unserialize(cp, section); }
343 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
345 Tick readLastActivate() { return actualTC->readLastActivate(); }
346 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
348 void profileClear() { return actualTC->profileClear(); }
349 void profileSample() { return actualTC->profileSample(); }
352 int getThreadNum() { return actualTC->getThreadNum(); }
354 // @todo: Do I need this?
355 MachInst getInst() { return actualTC->getInst(); }
357 // @todo: Do I need this?
358 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
360 void clearArchRegs() { actualTC->clearArchRegs(); }
363 // New accessors for new decoder.
365 uint64_t readIntReg(int reg_idx)
366 { return actualTC->readIntReg(reg_idx); }
368 FloatReg readFloatReg(int reg_idx, int width)
369 { return actualTC->readFloatReg(reg_idx, width); }
371 FloatReg readFloatReg(int reg_idx)
372 { return actualTC->readFloatReg(reg_idx); }
374 FloatRegBits readFloatRegBits(int reg_idx, int width)
375 { return actualTC->readFloatRegBits(reg_idx, width); }
377 FloatRegBits readFloatRegBits(int reg_idx)
378 { return actualTC->readFloatRegBits(reg_idx); }
380 void setIntReg(int reg_idx, uint64_t val)
381 { actualTC->setIntReg(reg_idx, val); }
383 void setFloatReg(int reg_idx, FloatReg val, int width)
384 { actualTC->setFloatReg(reg_idx, val, width); }
386 void setFloatReg(int reg_idx, FloatReg val)
387 { actualTC->setFloatReg(reg_idx, val); }
389 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
390 { actualTC->setFloatRegBits(reg_idx, val, width); }
392 void setFloatRegBits(int reg_idx, FloatRegBits val)
393 { actualTC->setFloatRegBits(reg_idx, val); }
395 uint64_t readPC() { return actualTC->readPC(); }
397 void setPC(uint64_t val) { actualTC->setPC(val); }
399 uint64_t readNextPC() { return actualTC->readNextPC(); }
401 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
403 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
405 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
407 MiscReg readMiscReg(int misc_reg)
408 { return actualTC->readMiscReg(misc_reg); }
410 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
411 { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
413 Fault setMiscReg(int misc_reg, const MiscReg &val)
414 { return actualTC->setMiscReg(misc_reg, val); }
416 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
417 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
419 unsigned readStCondFailures()
420 { return actualTC->readStCondFailures(); }
422 void setStCondFailures(unsigned sc_failures)
423 { actualTC->setStCondFailures(sc_failures); }
425 bool inPalMode() { return actualTC->inPalMode(); }
429 bool misspeculating() { return actualTC->misspeculating(); }
432 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
434 // used to shift args for indirect syscall
435 void setSyscallArg(int i, IntReg val)
436 { actualTC->setSyscallArg(i, val); }
438 void setSyscallReturn(SyscallReturn return_value)
439 { actualTC->setSyscallReturn(return_value); }
441 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
444 void changeRegFileContext(TheISA::RegContextParam param,
445 TheISA::RegContextVal val)
447 actualTC->changeRegFileContext(param, val);