src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include "arch/regfile.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "mem/request.hh"
  38 #include "sim/faults.hh"
  39 #include "sim/host.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/syscallreturn.hh"
  42 #include "sim/byteswap.hh"
  43
  44 // @todo: Figure out a more architecture independent way to obtain the ITB and
  45 // DTB pointers.
  46 namespace TheISA
  47 {
  48     class DTB;
  49     class ITB;
  50 }
  51 class BaseCPU;
  52 class EndQuiesceEvent;
  53 class Event;
  54 class TranslatingPort;
  55 class FunctionalPort;
  56 class VirtualPort;
  57 class Process;
  58 class System;
  59 namespace TheISA {
  60     namespace Kernel {
  61         class Statistics;
  62     };
  63 };
  64
  65 /**
  66  * ThreadContext is the external interface to all thread state for
  67  * anything outside of the CPU. It provides all accessor methods to
  68  * state that might be needed by external objects, ranging from
  69  * register values to things such as kernel stats. It is an abstract
  70  * base class; the CPU can create its own ThreadContext by either
  71  * deriving from it, or using the templated ProxyThreadContext.
  72  *
  73  * The ThreadContext is slightly different than the ExecContext.  The
  74  * ThreadContext provides access to an individual thread's state; an
  75  * ExecContext provides ISA access to the CPU (meaning it is
  76  * implicitly multithreaded on SMT systems).  Additionally the
  77  * ThreadState is an abstract class that exactly defines the
  78  * interface; the ExecContext is a more implicit interface that must
  79  * be implemented so that the ISA can access whatever state it needs.
  80  */
  81 class ThreadContext
  82 {
  83   protected:
  84     typedef TheISA::RegFile RegFile;
  85     typedef TheISA::MachInst MachInst;
  86     typedef TheISA::IntReg IntReg;
  87     typedef TheISA::FloatReg FloatReg;
  88     typedef TheISA::FloatRegBits FloatRegBits;
  89     typedef TheISA::MiscRegFile MiscRegFile;
  90     typedef TheISA::MiscReg MiscReg;
  91   public:
  92     enum Status
  93     {
  94         /// Initialized but not running yet.  All CPUs start in
  95         /// this state, but most transition to Active on cycle 1.
  96         /// In MP or SMT systems, non-primary contexts will stay
  97         /// in this state until a thread is assigned to them.
  98         Unallocated,
  99
 100         /// Running.  Instructions should be executed only when
 101         /// the context is in this state.
 102         Active,
 103
 104         /// Temporarily inactive.  Entered while waiting for
 105         /// synchronization, etc.
 106         Suspended,
 107
 108         /// Permanently shut down.  Entered when target executes
 109         /// m5exit pseudo-instruction.  When all contexts enter
 110         /// this state, the simulation will terminate.
 111         Halted
 112     };
 113
 114     virtual ~ThreadContext() { };
 115
 116     virtual BaseCPU *getCpuPtr() = 0;
 117
 118     virtual int cpuId() = 0;
 119
 120     virtual int threadId() = 0;
 121
 122     virtual void setThreadId(int id) = 0;
 123
 124     virtual int contextId() = 0;
 125
 126     virtual void setContextId(int id) = 0;
 127
 128     virtual TheISA::ITB *getITBPtr() = 0;
 129
 130     virtual TheISA::DTB *getDTBPtr() = 0;
 131
 132     virtual System *getSystemPtr() = 0;
 133
 134 #if FULL_SYSTEM
 135     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 136
 137     virtual FunctionalPort *getPhysPort() = 0;
 138
 139     virtual VirtualPort *getVirtPort() = 0;
 140
 141     virtual void connectMemPorts(ThreadContext *tc) = 0;
 142 #else
 143     virtual TranslatingPort *getMemPort() = 0;
 144
 145     virtual Process *getProcessPtr() = 0;
 146 #endif
 147
 148     virtual Status status() const = 0;
 149
 150     virtual void setStatus(Status new_status) = 0;
 151
 152     /// Set the status to Active.  Optional delay indicates number of
 153     /// cycles to wait before beginning execution.
 154     virtual void activate(int delay = 1) = 0;
 155
 156     /// Set the status to Suspended.
 157     virtual void suspend(int delay = 0) = 0;
 158
 159     /// Set the status to Unallocated.
 160     virtual void deallocate(int delay = 0) = 0;
 161
 162     /// Set the status to Halted.
 163     virtual void halt(int delay = 0) = 0;
 164
 165 #if FULL_SYSTEM
 166     virtual void dumpFuncProfile() = 0;
 167 #endif
 168
 169     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 170
 171     virtual void regStats(const std::string &name) = 0;
 172
 173     virtual void serialize(std::ostream &os) = 0;
 174     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 175
 176 #if FULL_SYSTEM
 177     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 178
 179     // Not necessarily the best location for these...
 180     // Having an extra function just to read these is obnoxious
 181     virtual Tick readLastActivate() = 0;
 182     virtual Tick readLastSuspend() = 0;
 183
 184     virtual void profileClear() = 0;
 185     virtual void profileSample() = 0;
 186 #endif
 187
 188     // Also somewhat obnoxious.  Really only used for the TLB fault.
 189     // However, may be quite useful in SPARC.
 190     virtual TheISA::MachInst getInst() = 0;
 191
 192     virtual void copyArchRegs(ThreadContext *tc) = 0;
 193
 194     virtual void clearArchRegs() = 0;
 195
 196     //
 197     // New accessors for new decoder.
 198     //
 199     virtual uint64_t readIntReg(int reg_idx) = 0;
 200
 201     virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
 202
 203     virtual FloatReg readFloatReg(int reg_idx) = 0;
 204
 205     virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
 206
 207     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 208
 209     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 210
 211     virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
 212
 213     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 214
 215     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 216
 217     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
 218
 219     virtual uint64_t readPC() = 0;
 220
 221     virtual void setPC(uint64_t val) = 0;
 222
 223     virtual uint64_t readNextPC() = 0;
 224
 225     virtual void setNextPC(uint64_t val) = 0;
 226
 227     virtual uint64_t readNextNPC() = 0;
 228
 229     virtual void setNextNPC(uint64_t val) = 0;
 230
 231     virtual uint64_t readMicroPC() = 0;
 232
 233     virtual void setMicroPC(uint64_t val) = 0;
 234
 235     virtual uint64_t readNextMicroPC() = 0;
 236
 237     virtual void setNextMicroPC(uint64_t val) = 0;
 238
 239     virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 240
 241     virtual MiscReg readMiscReg(int misc_reg) = 0;
 242
 243     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 244
 245     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 246
 247     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
 248
 249     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
 250
 251     // Also not necessarily the best location for these two.  Hopefully will go
 252     // away once we decide upon where st cond failures goes.
 253     virtual unsigned readStCondFailures() = 0;
 254
 255     virtual void setStCondFailures(unsigned sc_failures) = 0;
 256
 257     // Only really makes sense for old CPU model.  Still could be useful though.
 258     virtual bool misspeculating() = 0;
 259
 260 #if !FULL_SYSTEM
 261     virtual IntReg getSyscallArg(int i) = 0;
 262
 263     // used to shift args for indirect syscall
 264     virtual void setSyscallArg(int i, IntReg val) = 0;
 265
 266     virtual void setSyscallReturn(SyscallReturn return_value) = 0;
 267
 268     // Same with st cond failures.
 269     virtual Counter readFuncExeInst() = 0;
 270
 271     virtual void syscall(int64_t callnum) = 0;
 272
 273     // This function exits the thread context in the CPU and returns
 274     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 275     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 276     virtual int exit() { return 1; };
 277 #endif
 278
 279     /** function to compare two thread contexts (for debugging) */
 280     static void compare(ThreadContext *one, ThreadContext *two);
 281 };
 282
 283 /**
 284  * ProxyThreadContext class that provides a way to implement a
 285  * ThreadContext without having to derive from it. ThreadContext is an
 286  * abstract class, so anything that derives from it and uses its
 287  * interface will pay the overhead of virtual function calls.  This
 288  * class is created to enable a user-defined Thread object to be used
 289  * wherever ThreadContexts are used, without paying the overhead of
 290  * virtual function calls when it is used by itself.  See
 291  * simple_thread.hh for an example of this.
 292  */
 293 template <class TC>
 294 class ProxyThreadContext : public ThreadContext
 295 {
 296   public:
 297     ProxyThreadContext(TC *actual_tc)
 298     { actualTC = actual_tc; }
 299
 300   private:
 301     TC *actualTC;
 302
 303   public:
 304
 305     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 306
 307     int cpuId() { return actualTC->cpuId(); }
 308
 309     int threadId() { return actualTC->threadId(); }
 310
 311     void setThreadId(int id) { return actualTC->setThreadId(id); }
 312
 313     int contextId() { return actualTC->contextId(); }
 314
 315     void setContextId(int id) { actualTC->setContextId(id); }
 316
 317     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 318
 319     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 320
 321     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 322
 323 #if FULL_SYSTEM
 324     TheISA::Kernel::Statistics *getKernelStats()
 325     { return actualTC->getKernelStats(); }
 326
 327     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 328
 329     VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
 330
 331     void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 332 #else
 333     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 334
 335     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 336 #endif
 337
 338     Status status() const { return actualTC->status(); }
 339
 340     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 341
 342     /// Set the status to Active.  Optional delay indicates number of
 343     /// cycles to wait before beginning execution.
 344     void activate(int delay = 1) { actualTC->activate(delay); }
 345
 346     /// Set the status to Suspended.
 347     void suspend(int delay = 0) { actualTC->suspend(); }
 348
 349     /// Set the status to Unallocated.
 350     void deallocate(int delay = 0) { actualTC->deallocate(); }
 351
 352     /// Set the status to Halted.
 353     void halt(int delay = 0) { actualTC->halt(); }
 354
 355 #if FULL_SYSTEM
 356     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 357 #endif
 358
 359     void takeOverFrom(ThreadContext *oldContext)
 360     { actualTC->takeOverFrom(oldContext); }
 361
 362     void regStats(const std::string &name) { actualTC->regStats(name); }
 363
 364     void serialize(std::ostream &os) { actualTC->serialize(os); }
 365     void unserialize(Checkpoint *cp, const std::string &section)
 366     { actualTC->unserialize(cp, section); }
 367
 368 #if FULL_SYSTEM
 369     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 370
 371     Tick readLastActivate() { return actualTC->readLastActivate(); }
 372     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 373
 374     void profileClear() { return actualTC->profileClear(); }
 375     void profileSample() { return actualTC->profileSample(); }
 376 #endif
 377     // @todo: Do I need this?
 378     MachInst getInst() { return actualTC->getInst(); }
 379
 380     // @todo: Do I need this?
 381     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 382
 383     void clearArchRegs() { actualTC->clearArchRegs(); }
 384
 385     //
 386     // New accessors for new decoder.
 387     //
 388     uint64_t readIntReg(int reg_idx)
 389     { return actualTC->readIntReg(reg_idx); }
 390
 391     FloatReg readFloatReg(int reg_idx, int width)
 392     { return actualTC->readFloatReg(reg_idx, width); }
 393
 394     FloatReg readFloatReg(int reg_idx)
 395     { return actualTC->readFloatReg(reg_idx); }
 396
 397     FloatRegBits readFloatRegBits(int reg_idx, int width)
 398     { return actualTC->readFloatRegBits(reg_idx, width); }
 399
 400     FloatRegBits readFloatRegBits(int reg_idx)
 401     { return actualTC->readFloatRegBits(reg_idx); }
 402
 403     void setIntReg(int reg_idx, uint64_t val)
 404     { actualTC->setIntReg(reg_idx, val); }
 405
 406     void setFloatReg(int reg_idx, FloatReg val, int width)
 407     { actualTC->setFloatReg(reg_idx, val, width); }
 408
 409     void setFloatReg(int reg_idx, FloatReg val)
 410     { actualTC->setFloatReg(reg_idx, val); }
 411
 412     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 413     { actualTC->setFloatRegBits(reg_idx, val, width); }
 414
 415     void setFloatRegBits(int reg_idx, FloatRegBits val)
 416     { actualTC->setFloatRegBits(reg_idx, val); }
 417
 418     uint64_t readPC() { return actualTC->readPC(); }
 419
 420     void setPC(uint64_t val) { actualTC->setPC(val); }
 421
 422     uint64_t readNextPC() { return actualTC->readNextPC(); }
 423
 424     void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
 425
 426     uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 427
 428     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 429
 430     uint64_t readMicroPC() { return actualTC->readMicroPC(); }
 431
 432     void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
 433
 434     uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
 435
 436     void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
 437
 438     MiscReg readMiscRegNoEffect(int misc_reg)
 439     { return actualTC->readMiscRegNoEffect(misc_reg); }
 440
 441     MiscReg readMiscReg(int misc_reg)
 442     { return actualTC->readMiscReg(misc_reg); }
 443
 444     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 445     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 446
 447     void setMiscReg(int misc_reg, const MiscReg &val)
 448     { return actualTC->setMiscReg(misc_reg, val); }
 449
 450     unsigned readStCondFailures()
 451     { return actualTC->readStCondFailures(); }
 452
 453     void setStCondFailures(unsigned sc_failures)
 454     { actualTC->setStCondFailures(sc_failures); }
 455
 456     // @todo: Fix this!
 457     bool misspeculating() { return actualTC->misspeculating(); }
 458
 459 #if !FULL_SYSTEM
 460     IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
 461
 462     // used to shift args for indirect syscall
 463     void setSyscallArg(int i, IntReg val)
 464     { actualTC->setSyscallArg(i, val); }
 465
 466     void setSyscallReturn(SyscallReturn return_value)
 467     { actualTC->setSyscallReturn(return_value); }
 468
 469     void syscall(int64_t callnum)
 470     { actualTC->syscall(callnum); }
 471
 472     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 473 #endif
 474 };
 475
 476 #endif