src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include "arch/regfile.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "mem/request.hh"
  38 #include "sim/faults.hh"
  39 #include "sim/host.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/syscallreturn.hh"
  42 #include "sim/byteswap.hh"
  43
  44 // @todo: Figure out a more architecture independent way to obtain the ITB and
  45 // DTB pointers.
  46 namespace TheISA
  47 {
  48     class DTB;
  49     class ITB;
  50 }
  51 class BaseCPU;
  52 class EndQuiesceEvent;
  53 class Event;
  54 class TranslatingPort;
  55 class FunctionalPort;
  56 class VirtualPort;
  57 class Process;
  58 class System;
  59 namespace TheISA {
  60     namespace Kernel {
  61         class Statistics;
  62     };
  63 };
  64
  65 /**
  66  * ThreadContext is the external interface to all thread state for
  67  * anything outside of the CPU. It provides all accessor methods to
  68  * state that might be needed by external objects, ranging from
  69  * register values to things such as kernel stats. It is an abstract
  70  * base class; the CPU can create its own ThreadContext by either
  71  * deriving from it, or using the templated ProxyThreadContext.
  72  *
  73  * The ThreadContext is slightly different than the ExecContext.  The
  74  * ThreadContext provides access to an individual thread's state; an
  75  * ExecContext provides ISA access to the CPU (meaning it is
  76  * implicitly multithreaded on SMT systems).  Additionally the
  77  * ThreadState is an abstract class that exactly defines the
  78  * interface; the ExecContext is a more implicit interface that must
  79  * be implemented so that the ISA can access whatever state it needs.
  80  */
  81 class ThreadContext
  82 {
  83   protected:
  84     typedef TheISA::RegFile RegFile;
  85     typedef TheISA::MachInst MachInst;
  86     typedef TheISA::IntReg IntReg;
  87     typedef TheISA::FloatReg FloatReg;
  88     typedef TheISA::FloatRegBits FloatRegBits;
  89     typedef TheISA::MiscRegFile MiscRegFile;
  90     typedef TheISA::MiscReg MiscReg;
  91   public:
  92     enum Status
  93     {
  94         /// Initialized but not running yet.  All CPUs start in
  95         /// this state, but most transition to Active on cycle 1.
  96         /// In MP or SMT systems, non-primary contexts will stay
  97         /// in this state until a thread is assigned to them.
  98         Unallocated,
  99
 100         /// Running.  Instructions should be executed only when
 101         /// the context is in this state.
 102         Active,
 103
 104         /// Temporarily inactive.  Entered while waiting for
 105         /// synchronization, etc.
 106         Suspended,
 107
 108         /// Permanently shut down.  Entered when target executes
 109         /// m5exit pseudo-instruction.  When all contexts enter
 110         /// this state, the simulation will terminate.
 111         Halted
 112     };
 113
 114     virtual ~ThreadContext() { };
 115
 116     virtual BaseCPU *getCpuPtr() = 0;
 117
 118     virtual void setCpuId(int id) = 0;
 119
 120     virtual int readCpuId() = 0;
 121
 122     virtual TheISA::ITB *getITBPtr() = 0;
 123
 124     virtual TheISA::DTB *getDTBPtr() = 0;
 125
 126 #if FULL_SYSTEM
 127     virtual System *getSystemPtr() = 0;
 128
 129     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 130
 131     virtual FunctionalPort *getPhysPort() = 0;
 132
 133     virtual VirtualPort *getVirtPort() = 0;
 134
 135     virtual void connectMemPorts(ThreadContext *tc) = 0;
 136 #else
 137     virtual TranslatingPort *getMemPort() = 0;
 138
 139     virtual Process *getProcessPtr() = 0;
 140 #endif
 141
 142     virtual Status status() const = 0;
 143
 144     virtual void setStatus(Status new_status) = 0;
 145
 146     /// Set the status to Active.  Optional delay indicates number of
 147     /// cycles to wait before beginning execution.
 148     virtual void activate(int delay = 1) = 0;
 149
 150     /// Set the status to Suspended.
 151     virtual void suspend(int delay = 0) = 0;
 152
 153     /// Set the status to Unallocated.
 154     virtual void deallocate(int delay = 0) = 0;
 155
 156     /// Set the status to Halted.
 157     virtual void halt(int delay = 0) = 0;
 158
 159 #if FULL_SYSTEM
 160     virtual void dumpFuncProfile() = 0;
 161 #endif
 162
 163     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 164
 165     virtual void regStats(const std::string &name) = 0;
 166
 167     virtual void serialize(std::ostream &os) = 0;
 168     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 169
 170 #if FULL_SYSTEM
 171     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 172
 173     // Not necessarily the best location for these...
 174     // Having an extra function just to read these is obnoxious
 175     virtual Tick readLastActivate() = 0;
 176     virtual Tick readLastSuspend() = 0;
 177
 178     virtual void profileClear() = 0;
 179     virtual void profileSample() = 0;
 180 #endif
 181
 182     virtual int getThreadNum() = 0;
 183
 184     // Also somewhat obnoxious.  Really only used for the TLB fault.
 185     // However, may be quite useful in SPARC.
 186     virtual TheISA::MachInst getInst() = 0;
 187
 188     virtual void copyArchRegs(ThreadContext *tc) = 0;
 189
 190     virtual void clearArchRegs() = 0;
 191
 192     //
 193     // New accessors for new decoder.
 194     //
 195     virtual uint64_t readIntReg(int reg_idx) = 0;
 196
 197     virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
 198
 199     virtual FloatReg readFloatReg(int reg_idx) = 0;
 200
 201     virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
 202
 203     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 204
 205     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 206
 207     virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
 208
 209     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 210
 211     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 212
 213     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
 214
 215     virtual uint64_t readPC() = 0;
 216
 217     virtual void setPC(uint64_t val) = 0;
 218
 219     virtual uint64_t readNextPC() = 0;
 220
 221     virtual void setNextPC(uint64_t val) = 0;
 222
 223     virtual uint64_t readNextNPC() = 0;
 224
 225     virtual void setNextNPC(uint64_t val) = 0;
 226
 227     virtual uint64_t readMicroPC() = 0;
 228
 229     virtual void setMicroPC(uint64_t val) = 0;
 230
 231     virtual uint64_t readNextMicroPC() = 0;
 232
 233     virtual void setNextMicroPC(uint64_t val) = 0;
 234
 235     virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 236
 237     virtual MiscReg readMiscReg(int misc_reg) = 0;
 238
 239     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 240
 241     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 242
 243     virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
 244
 245     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
 246
 247     // Also not necessarily the best location for these two.  Hopefully will go
 248     // away once we decide upon where st cond failures goes.
 249     virtual unsigned readStCondFailures() = 0;
 250
 251     virtual void setStCondFailures(unsigned sc_failures) = 0;
 252
 253     // Only really makes sense for old CPU model.  Still could be useful though.
 254     virtual bool misspeculating() = 0;
 255
 256 #if !FULL_SYSTEM
 257     virtual IntReg getSyscallArg(int i) = 0;
 258
 259     // used to shift args for indirect syscall
 260     virtual void setSyscallArg(int i, IntReg val) = 0;
 261
 262     virtual void setSyscallReturn(SyscallReturn return_value) = 0;
 263
 264     // Same with st cond failures.
 265     virtual Counter readFuncExeInst() = 0;
 266
 267     virtual void syscall(int64_t callnum) = 0;
 268
 269     // This function exits the thread context in the CPU and returns
 270     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 271     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 272     virtual int exit() { return 1; };
 273 #endif
 274
 275     virtual void changeRegFileContext(TheISA::RegContextParam param,
 276             TheISA::RegContextVal val) = 0;
 277
 278     /** function to compare two thread contexts (for debugging) */
 279     static void compare(ThreadContext *one, ThreadContext *two);
 280 };
 281
 282 /**
 283  * ProxyThreadContext class that provides a way to implement a
 284  * ThreadContext without having to derive from it. ThreadContext is an
 285  * abstract class, so anything that derives from it and uses its
 286  * interface will pay the overhead of virtual function calls.  This
 287  * class is created to enable a user-defined Thread object to be used
 288  * wherever ThreadContexts are used, without paying the overhead of
 289  * virtual function calls when it is used by itself.  See
 290  * simple_thread.hh for an example of this.
 291  */
 292 template <class TC>
 293 class ProxyThreadContext : public ThreadContext
 294 {
 295   public:
 296     ProxyThreadContext(TC *actual_tc)
 297     { actualTC = actual_tc; }
 298
 299   private:
 300     TC *actualTC;
 301
 302   public:
 303
 304     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 305
 306     void setCpuId(int id) { actualTC->setCpuId(id); }
 307
 308     int readCpuId() { return actualTC->readCpuId(); }
 309
 310     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 311
 312     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 313
 314 #if FULL_SYSTEM
 315     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 316
 317     TheISA::Kernel::Statistics *getKernelStats()
 318     { return actualTC->getKernelStats(); }
 319
 320     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 321
 322     VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
 323
 324     void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 325 #else
 326     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 327
 328     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 329 #endif
 330
 331     Status status() const { return actualTC->status(); }
 332
 333     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 334
 335     /// Set the status to Active.  Optional delay indicates number of
 336     /// cycles to wait before beginning execution.
 337     void activate(int delay = 1) { actualTC->activate(delay); }
 338
 339     /// Set the status to Suspended.
 340     void suspend(int delay = 0) { actualTC->suspend(); }
 341
 342     /// Set the status to Unallocated.
 343     void deallocate(int delay = 0) { actualTC->deallocate(); }
 344
 345     /// Set the status to Halted.
 346     void halt(int delay = 0) { actualTC->halt(); }
 347
 348 #if FULL_SYSTEM
 349     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 350 #endif
 351
 352     void takeOverFrom(ThreadContext *oldContext)
 353     { actualTC->takeOverFrom(oldContext); }
 354
 355     void regStats(const std::string &name) { actualTC->regStats(name); }
 356
 357     void serialize(std::ostream &os) { actualTC->serialize(os); }
 358     void unserialize(Checkpoint *cp, const std::string &section)
 359     { actualTC->unserialize(cp, section); }
 360
 361 #if FULL_SYSTEM
 362     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 363
 364     Tick readLastActivate() { return actualTC->readLastActivate(); }
 365     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 366
 367     void profileClear() { return actualTC->profileClear(); }
 368     void profileSample() { return actualTC->profileSample(); }
 369 #endif
 370
 371     int getThreadNum() { return actualTC->getThreadNum(); }
 372
 373     // @todo: Do I need this?
 374     MachInst getInst() { return actualTC->getInst(); }
 375
 376     // @todo: Do I need this?
 377     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 378
 379     void clearArchRegs() { actualTC->clearArchRegs(); }
 380
 381     //
 382     // New accessors for new decoder.
 383     //
 384     uint64_t readIntReg(int reg_idx)
 385     { return actualTC->readIntReg(reg_idx); }
 386
 387     FloatReg readFloatReg(int reg_idx, int width)
 388     { return actualTC->readFloatReg(reg_idx, width); }
 389
 390     FloatReg readFloatReg(int reg_idx)
 391     { return actualTC->readFloatReg(reg_idx); }
 392
 393     FloatRegBits readFloatRegBits(int reg_idx, int width)
 394     { return actualTC->readFloatRegBits(reg_idx, width); }
 395
 396     FloatRegBits readFloatRegBits(int reg_idx)
 397     { return actualTC->readFloatRegBits(reg_idx); }
 398
 399     void setIntReg(int reg_idx, uint64_t val)
 400     { actualTC->setIntReg(reg_idx, val); }
 401
 402     void setFloatReg(int reg_idx, FloatReg val, int width)
 403     { actualTC->setFloatReg(reg_idx, val, width); }
 404
 405     void setFloatReg(int reg_idx, FloatReg val)
 406     { actualTC->setFloatReg(reg_idx, val); }
 407
 408     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 409     { actualTC->setFloatRegBits(reg_idx, val, width); }
 410
 411     void setFloatRegBits(int reg_idx, FloatRegBits val)
 412     { actualTC->setFloatRegBits(reg_idx, val); }
 413
 414     uint64_t readPC() { return actualTC->readPC(); }
 415
 416     void setPC(uint64_t val) { actualTC->setPC(val); }
 417
 418     uint64_t readNextPC() { return actualTC->readNextPC(); }
 419
 420     void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
 421
 422     uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 423
 424     void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 425
 426     uint64_t readMicroPC() { return actualTC->readMicroPC(); }
 427
 428     void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
 429
 430     uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
 431
 432     void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
 433
 434     MiscReg readMiscRegNoEffect(int misc_reg)
 435     { return actualTC->readMiscRegNoEffect(misc_reg); }
 436
 437     MiscReg readMiscReg(int misc_reg)
 438     { return actualTC->readMiscReg(misc_reg); }
 439
 440     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 441     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 442
 443     void setMiscReg(int misc_reg, const MiscReg &val)
 444     { return actualTC->setMiscReg(misc_reg, val); }
 445
 446     unsigned readStCondFailures()
 447     { return actualTC->readStCondFailures(); }
 448
 449     void setStCondFailures(unsigned sc_failures)
 450     { actualTC->setStCondFailures(sc_failures); }
 451
 452     // @todo: Fix this!
 453     bool misspeculating() { return actualTC->misspeculating(); }
 454
 455 #if !FULL_SYSTEM
 456     IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
 457
 458     // used to shift args for indirect syscall
 459     void setSyscallArg(int i, IntReg val)
 460     { actualTC->setSyscallArg(i, val); }
 461
 462     void setSyscallReturn(SyscallReturn return_value)
 463     { actualTC->setSyscallReturn(return_value); }
 464
 465     void syscall(int64_t callnum)
 466     { actualTC->syscall(callnum); }
 467
 468     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 469 #endif
 470
 471     void changeRegFileContext(TheISA::RegContextParam param,
 472             TheISA::RegContextVal val)
 473     {
 474         actualTC->changeRegFileContext(param, val);
 475     }
 476 };
 477
 478 #endif