src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_THREAD_CONTEXT_HH__
  45 #define __CPU_THREAD_CONTEXT_HH__
  46
  47 #include <iostream>
  48 #include <string>
  49
  50 #include "arch/registers.hh"
  51 #include "arch/types.hh"
  52 #include "base/types.hh"
  53 #include "config/the_isa.hh"
  54
  55 // @todo: Figure out a more architecture independent way to obtain the ITB and
  56 // DTB pointers.
  57 namespace TheISA
  58 {
  59     class Decoder;
  60     class TLB;
  61 }
  62 class BaseCPU;
  63 class CheckerCPU;
  64 class Checkpoint;
  65 class EndQuiesceEvent;
  66 class SETranslatingPortProxy;
  67 class FSTranslatingPortProxy;
  68 class PortProxy;
  69 class Process;
  70 class System;
  71 namespace TheISA {
  72     namespace Kernel {
  73         class Statistics;
  74     }
  75 }
  76
  77 /**
  78  * ThreadContext is the external interface to all thread state for
  79  * anything outside of the CPU. It provides all accessor methods to
  80  * state that might be needed by external objects, ranging from
  81  * register values to things such as kernel stats. It is an abstract
  82  * base class; the CPU can create its own ThreadContext by either
  83  * deriving from it, or using the templated ProxyThreadContext.
  84  *
  85  * The ThreadContext is slightly different than the ExecContext.  The
  86  * ThreadContext provides access to an individual thread's state; an
  87  * ExecContext provides ISA access to the CPU (meaning it is
  88  * implicitly multithreaded on SMT systems).  Additionally the
  89  * ThreadState is an abstract class that exactly defines the
  90  * interface; the ExecContext is a more implicit interface that must
  91  * be implemented so that the ISA can access whatever state it needs.
  92  */
  93 class ThreadContext
  94 {
  95   protected:
  96     typedef TheISA::MachInst MachInst;
  97     typedef TheISA::IntReg IntReg;
  98     typedef TheISA::FloatReg FloatReg;
  99     typedef TheISA::FloatRegBits FloatRegBits;
 100     typedef TheISA::CCReg CCReg;
 101     typedef TheISA::MiscReg MiscReg;
 102   public:
 103
 104     enum Status
 105     {
 106         /// Running.  Instructions should be executed only when
 107         /// the context is in this state.
 108         Active,
 109
 110         /// Temporarily inactive.  Entered while waiting for
 111         /// synchronization, etc.
 112         Suspended,
 113
 114         /// Permanently shut down.  Entered when target executes
 115         /// m5exit pseudo-instruction.  When all contexts enter
 116         /// this state, the simulation will terminate.
 117         Halted
 118     };
 119
 120     virtual ~ThreadContext() { };
 121
 122     virtual BaseCPU *getCpuPtr() = 0;
 123
 124     virtual int cpuId() const = 0;
 125
 126     virtual uint32_t socketId() const = 0;
 127
 128     virtual int threadId() const = 0;
 129
 130     virtual void setThreadId(int id) = 0;
 131
 132     virtual int contextId() const = 0;
 133
 134     virtual void setContextId(int id) = 0;
 135
 136     virtual TheISA::TLB *getITBPtr() = 0;
 137
 138     virtual TheISA::TLB *getDTBPtr() = 0;
 139
 140     virtual CheckerCPU *getCheckerCpuPtr() = 0;
 141
 142     virtual TheISA::Decoder *getDecoderPtr() = 0;
 143
 144     virtual System *getSystemPtr() = 0;
 145
 146     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 147
 148     virtual PortProxy &getPhysProxy() = 0;
 149
 150     virtual FSTranslatingPortProxy &getVirtProxy() = 0;
 151
 152     /**
 153      * Initialise the physical and virtual port proxies and tie them to
 154      * the data port of the CPU.
 155      *
 156      * tc ThreadContext for the virtual-to-physical translation
 157      */
 158     virtual void initMemProxies(ThreadContext *tc) = 0;
 159
 160     virtual SETranslatingPortProxy &getMemProxy() = 0;
 161
 162     virtual Process *getProcessPtr() = 0;
 163
 164     virtual void setProcessPtr(Process *p) = 0;
 165
 166     virtual Status status() const = 0;
 167
 168     virtual void setStatus(Status new_status) = 0;
 169
 170     /// Set the status to Active.
 171     virtual void activate() = 0;
 172
 173     /// Set the status to Suspended.
 174     virtual void suspend() = 0;
 175
 176     /// Set the status to Halted.
 177     virtual void halt() = 0;
 178
 179     /// Quiesce thread context
 180     void quiesce();
 181
 182     /// Quiesce, suspend, and schedule activate at resume
 183     void quiesceTick(Tick resume);
 184
 185     virtual void dumpFuncProfile() = 0;
 186
 187     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 188
 189     virtual void regStats(const std::string &name) = 0;
 190
 191     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 192
 193     // Not necessarily the best location for these...
 194     // Having an extra function just to read these is obnoxious
 195     virtual Tick readLastActivate() = 0;
 196     virtual Tick readLastSuspend() = 0;
 197
 198     virtual void profileClear() = 0;
 199     virtual void profileSample() = 0;
 200
 201     virtual void copyArchRegs(ThreadContext *tc) = 0;
 202
 203     virtual void clearArchRegs() = 0;
 204
 205     //
 206     // New accessors for new decoder.
 207     //
 208     virtual uint64_t readIntReg(int reg_idx) = 0;
 209
 210     virtual FloatReg readFloatReg(int reg_idx) = 0;
 211
 212     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 213
 214     virtual CCReg readCCReg(int reg_idx) = 0;
 215
 216     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 217
 218     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 219
 220     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 221
 222     virtual void setCCReg(int reg_idx, CCReg val) = 0;
 223
 224     virtual TheISA::PCState pcState() = 0;
 225
 226     virtual void pcState(const TheISA::PCState &val) = 0;
 227
 228     void
 229     setNPC(Addr val)
 230     {
 231         TheISA::PCState pc_state = pcState();
 232         pc_state.setNPC(val);
 233         pcState(pc_state);
 234     }
 235
 236     virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 237
 238     virtual Addr instAddr() = 0;
 239
 240     virtual Addr nextInstAddr() = 0;
 241
 242     virtual MicroPC microPC() = 0;
 243
 244     virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
 245
 246     virtual MiscReg readMiscReg(int misc_reg) = 0;
 247
 248     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 249
 250     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 251
 252     virtual int flattenIntIndex(int reg) = 0;
 253     virtual int flattenFloatIndex(int reg) = 0;
 254     virtual int flattenCCIndex(int reg) = 0;
 255     virtual int flattenMiscIndex(int reg) = 0;
 256
 257     virtual uint64_t
 258     readRegOtherThread(int misc_reg, ThreadID tid)
 259     {
 260         return 0;
 261     }
 262
 263     virtual void
 264     setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
 265     {
 266     }
 267
 268     // Also not necessarily the best location for these two.  Hopefully will go
 269     // away once we decide upon where st cond failures goes.
 270     virtual unsigned readStCondFailures() = 0;
 271
 272     virtual void setStCondFailures(unsigned sc_failures) = 0;
 273
 274     // Same with st cond failures.
 275     virtual Counter readFuncExeInst() = 0;
 276
 277     virtual void syscall(int64_t callnum, Fault *fault) = 0;
 278
 279     // This function exits the thread context in the CPU and returns
 280     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 281     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 282     virtual int exit() { return 1; };
 283
 284     /** function to compare two thread contexts (for debugging) */
 285     static void compare(ThreadContext *one, ThreadContext *two);
 286
 287     /** @{ */
 288     /**
 289      * Flat register interfaces
 290      *
 291      * Some architectures have different registers visible in
 292      * different modes. Such architectures "flatten" a register (see
 293      * flattenIntIndex() and flattenFloatIndex()) to map it into the
 294      * gem5 register file. This interface provides a flat interface to
 295      * the underlying register file, which allows for example
 296      * serialization code to access all registers.
 297      */
 298
 299     virtual uint64_t readIntRegFlat(int idx) = 0;
 300     virtual void setIntRegFlat(int idx, uint64_t val) = 0;
 301
 302     virtual FloatReg readFloatRegFlat(int idx) = 0;
 303     virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
 304
 305     virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
 306     virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
 307
 308     virtual CCReg readCCRegFlat(int idx) = 0;
 309     virtual void setCCRegFlat(int idx, CCReg val) = 0;
 310     /** @} */
 311
 312 };
 313
 314 /**
 315  * ProxyThreadContext class that provides a way to implement a
 316  * ThreadContext without having to derive from it. ThreadContext is an
 317  * abstract class, so anything that derives from it and uses its
 318  * interface will pay the overhead of virtual function calls.  This
 319  * class is created to enable a user-defined Thread object to be used
 320  * wherever ThreadContexts are used, without paying the overhead of
 321  * virtual function calls when it is used by itself.  See
 322  * simple_thread.hh for an example of this.
 323  */
 324 template <class TC>
 325 class ProxyThreadContext : public ThreadContext
 326 {
 327   public:
 328     ProxyThreadContext(TC *actual_tc)
 329     { actualTC = actual_tc; }
 330
 331   private:
 332     TC *actualTC;
 333
 334   public:
 335
 336     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 337
 338     int cpuId() const { return actualTC->cpuId(); }
 339
 340     uint32_t socketId() const { return actualTC->socketId(); }
 341
 342     int threadId() const { return actualTC->threadId(); }
 343
 344     void setThreadId(int id) { actualTC->setThreadId(id); }
 345
 346     int contextId() const { return actualTC->contextId(); }
 347
 348     void setContextId(int id) { actualTC->setContextId(id); }
 349
 350     TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 351
 352     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 353
 354     CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
 355
 356     TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 357
 358     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 359
 360     TheISA::Kernel::Statistics *getKernelStats()
 361     { return actualTC->getKernelStats(); }
 362
 363     PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
 364
 365     FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
 366
 367     void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
 368
 369     SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
 370
 371     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 372
 373     void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
 374
 375     Status status() const { return actualTC->status(); }
 376
 377     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 378
 379     /// Set the status to Active.
 380     void activate() { actualTC->activate(); }
 381
 382     /// Set the status to Suspended.
 383     void suspend() { actualTC->suspend(); }
 384
 385     /// Set the status to Halted.
 386     void halt() { actualTC->halt(); }
 387
 388     /// Quiesce thread context
 389     void quiesce() { actualTC->quiesce(); }
 390
 391     /// Quiesce, suspend, and schedule activate at resume
 392     void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
 393
 394     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 395
 396     void takeOverFrom(ThreadContext *oldContext)
 397     { actualTC->takeOverFrom(oldContext); }
 398
 399     void regStats(const std::string &name) { actualTC->regStats(name); }
 400
 401     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 402
 403     Tick readLastActivate() { return actualTC->readLastActivate(); }
 404     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 405
 406     void profileClear() { return actualTC->profileClear(); }
 407     void profileSample() { return actualTC->profileSample(); }
 408
 409     // @todo: Do I need this?
 410     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 411
 412     void clearArchRegs() { actualTC->clearArchRegs(); }
 413
 414     //
 415     // New accessors for new decoder.
 416     //
 417     uint64_t readIntReg(int reg_idx)
 418     { return actualTC->readIntReg(reg_idx); }
 419
 420     FloatReg readFloatReg(int reg_idx)
 421     { return actualTC->readFloatReg(reg_idx); }
 422
 423     FloatRegBits readFloatRegBits(int reg_idx)
 424     { return actualTC->readFloatRegBits(reg_idx); }
 425
 426     CCReg readCCReg(int reg_idx)
 427     { return actualTC->readCCReg(reg_idx); }
 428
 429     void setIntReg(int reg_idx, uint64_t val)
 430     { actualTC->setIntReg(reg_idx, val); }
 431
 432     void setFloatReg(int reg_idx, FloatReg val)
 433     { actualTC->setFloatReg(reg_idx, val); }
 434
 435     void setFloatRegBits(int reg_idx, FloatRegBits val)
 436     { actualTC->setFloatRegBits(reg_idx, val); }
 437
 438     void setCCReg(int reg_idx, CCReg val)
 439     { actualTC->setCCReg(reg_idx, val); }
 440
 441     TheISA::PCState pcState() { return actualTC->pcState(); }
 442
 443     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 444
 445     void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
 446
 447     Addr instAddr() { return actualTC->instAddr(); }
 448     Addr nextInstAddr() { return actualTC->nextInstAddr(); }
 449     MicroPC microPC() { return actualTC->microPC(); }
 450
 451     bool readPredicate() { return actualTC->readPredicate(); }
 452
 453     void setPredicate(bool val)
 454     { actualTC->setPredicate(val); }
 455
 456     MiscReg readMiscRegNoEffect(int misc_reg) const
 457     { return actualTC->readMiscRegNoEffect(misc_reg); }
 458
 459     MiscReg readMiscReg(int misc_reg)
 460     { return actualTC->readMiscReg(misc_reg); }
 461
 462     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 463     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 464
 465     void setMiscReg(int misc_reg, const MiscReg &val)
 466     { return actualTC->setMiscReg(misc_reg, val); }
 467
 468     int flattenIntIndex(int reg)
 469     { return actualTC->flattenIntIndex(reg); }
 470
 471     int flattenFloatIndex(int reg)
 472     { return actualTC->flattenFloatIndex(reg); }
 473
 474     int flattenCCIndex(int reg)
 475     { return actualTC->flattenCCIndex(reg); }
 476
 477     int flattenMiscIndex(int reg)
 478     { return actualTC->flattenMiscIndex(reg); }
 479
 480     unsigned readStCondFailures()
 481     { return actualTC->readStCondFailures(); }
 482
 483     void setStCondFailures(unsigned sc_failures)
 484     { actualTC->setStCondFailures(sc_failures); }
 485
 486     void syscall(int64_t callnum, Fault *fault)
 487     { actualTC->syscall(callnum, fault); }
 488
 489     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 490
 491     uint64_t readIntRegFlat(int idx)
 492     { return actualTC->readIntRegFlat(idx); }
 493
 494     void setIntRegFlat(int idx, uint64_t val)
 495     { actualTC->setIntRegFlat(idx, val); }
 496
 497     FloatReg readFloatRegFlat(int idx)
 498     { return actualTC->readFloatRegFlat(idx); }
 499
 500     void setFloatRegFlat(int idx, FloatReg val)
 501     { actualTC->setFloatRegFlat(idx, val); }
 502
 503     FloatRegBits readFloatRegBitsFlat(int idx)
 504     { return actualTC->readFloatRegBitsFlat(idx); }
 505
 506     void setFloatRegBitsFlat(int idx, FloatRegBits val)
 507     { actualTC->setFloatRegBitsFlat(idx, val); }
 508
 509     CCReg readCCRegFlat(int idx)
 510     { return actualTC->readCCRegFlat(idx); }
 511
 512     void setCCRegFlat(int idx, CCReg val)
 513     { actualTC->setCCRegFlat(idx, val); }
 514 };
 515
 516 /** @{ */
 517 /**
 518  * Thread context serialization helpers
 519  *
 520  * These helper functions provide a way to the data in a
 521  * ThreadContext. They are provided as separate helper function since
 522  * implementing them as members of the ThreadContext interface would
 523  * be confusing when the ThreadContext is exported via a proxy.
 524  */
 525
 526 void serialize(ThreadContext &tc, CheckpointOut &cp);
 527 void unserialize(ThreadContext &tc, CheckpointIn &cp);
 528
 529 /** @} */
 530
 531
 532 /**
 533  * Copy state between thread contexts in preparation for CPU handover.
 534  *
 535  * @note This method modifies the old thread contexts as well as the
 536  * new thread context. The old thread context will have its quiesce
 537  * event descheduled if it is scheduled and its status set to halted.
 538  *
 539  * @param new_tc Destination ThreadContext.
 540  * @param old_tc Source ThreadContext.
 541  */
 542 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
 543
 544 #endif