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43 #ifndef __CPU_THREAD_CONTEXT_HH__
44 #define __CPU_THREAD_CONTEXT_HH__
49 #include "arch/registers.hh"
50 #include "arch/types.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
54 // @todo: Figure out a more architecture independent way to obtain the ITB and
64 class EndQuiesceEvent;
65 class SETranslatingPortProxy;
66 class FSTranslatingPortProxy;
77 * ThreadContext is the external interface to all thread state for
78 * anything outside of the CPU. It provides all accessor methods to
79 * state that might be needed by external objects, ranging from
80 * register values to things such as kernel stats. It is an abstract
81 * base class; the CPU can create its own ThreadContext by either
82 * deriving from it, or using the templated ProxyThreadContext.
84 * The ThreadContext is slightly different than the ExecContext. The
85 * ThreadContext provides access to an individual thread's state; an
86 * ExecContext provides ISA access to the CPU (meaning it is
87 * implicitly multithreaded on SMT systems). Additionally the
88 * ThreadState is an abstract class that exactly defines the
89 * interface; the ExecContext is a more implicit interface that must
90 * be implemented so that the ISA can access whatever state it needs.
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::IntReg IntReg;
97 typedef TheISA::FloatReg FloatReg;
98 typedef TheISA::FloatRegBits FloatRegBits;
99 typedef TheISA::MiscReg MiscReg;
104 /// Running. Instructions should be executed only when
105 /// the context is in this state.
108 /// Temporarily inactive. Entered while waiting for
109 /// synchronization, etc.
112 /// Permanently shut down. Entered when target executes
113 /// m5exit pseudo-instruction. When all contexts enter
114 /// this state, the simulation will terminate.
118 virtual ~ThreadContext() { };
120 virtual BaseCPU *getCpuPtr() = 0;
122 virtual int cpuId() = 0;
124 virtual int threadId() = 0;
126 virtual void setThreadId(int id) = 0;
128 virtual int contextId() = 0;
130 virtual void setContextId(int id) = 0;
132 virtual TheISA::TLB *getITBPtr() = 0;
134 virtual TheISA::TLB *getDTBPtr() = 0;
136 virtual CheckerCPU *getCheckerCpuPtr() = 0;
138 virtual TheISA::Decoder *getDecoderPtr() = 0;
140 virtual System *getSystemPtr() = 0;
142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
144 virtual PortProxy &getPhysProxy() = 0;
146 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
149 * Initialise the physical and virtual port proxies and tie them to
150 * the data port of the CPU.
152 * tc ThreadContext for the virtual-to-physical translation
154 virtual void initMemProxies(ThreadContext *tc) = 0;
156 virtual SETranslatingPortProxy &getMemProxy() = 0;
158 virtual Process *getProcessPtr() = 0;
160 virtual Status status() const = 0;
162 virtual void setStatus(Status new_status) = 0;
164 /// Set the status to Active. Optional delay indicates number of
165 /// cycles to wait before beginning execution.
166 virtual void activate(Cycles delay = Cycles(1)) = 0;
168 /// Set the status to Suspended.
169 virtual void suspend(Cycles delay = Cycles(0)) = 0;
171 /// Set the status to Halted.
172 virtual void halt(Cycles delay = Cycles(0)) = 0;
174 virtual void dumpFuncProfile() = 0;
176 virtual void takeOverFrom(ThreadContext *old_context) = 0;
178 virtual void regStats(const std::string &name) = 0;
180 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
182 // Not necessarily the best location for these...
183 // Having an extra function just to read these is obnoxious
184 virtual Tick readLastActivate() = 0;
185 virtual Tick readLastSuspend() = 0;
187 virtual void profileClear() = 0;
188 virtual void profileSample() = 0;
190 virtual void copyArchRegs(ThreadContext *tc) = 0;
192 virtual void clearArchRegs() = 0;
195 // New accessors for new decoder.
197 virtual uint64_t readIntReg(int reg_idx) = 0;
199 virtual FloatReg readFloatReg(int reg_idx) = 0;
201 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
203 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
205 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
209 virtual TheISA::PCState pcState() = 0;
211 virtual void pcState(const TheISA::PCState &val) = 0;
213 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
215 virtual Addr instAddr() = 0;
217 virtual Addr nextInstAddr() = 0;
219 virtual MicroPC microPC() = 0;
221 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
223 virtual MiscReg readMiscReg(int misc_reg) = 0;
225 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
227 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
229 virtual int flattenIntIndex(int reg) = 0;
230 virtual int flattenFloatIndex(int reg) = 0;
233 readRegOtherThread(int misc_reg, ThreadID tid)
239 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
243 // Also not necessarily the best location for these two. Hopefully will go
244 // away once we decide upon where st cond failures goes.
245 virtual unsigned readStCondFailures() = 0;
247 virtual void setStCondFailures(unsigned sc_failures) = 0;
249 // Only really makes sense for old CPU model. Still could be useful though.
250 virtual bool misspeculating() = 0;
252 // Same with st cond failures.
253 virtual Counter readFuncExeInst() = 0;
255 virtual void syscall(int64_t callnum) = 0;
257 // This function exits the thread context in the CPU and returns
258 // 1 if the CPU has no more active threads (meaning it's OK to exit);
259 // Used in syscall-emulation mode when a thread calls the exit syscall.
260 virtual int exit() { return 1; };
262 /** function to compare two thread contexts (for debugging) */
263 static void compare(ThreadContext *one, ThreadContext *two);
267 * Flat register interfaces
269 * Some architectures have different registers visible in
270 * different modes. Such architectures "flatten" a register (see
271 * flattenIntIndex() and flattenFloatIndex()) to map it into the
272 * gem5 register file. This interface provides a flat interface to
273 * the underlying register file, which allows for example
274 * serialization code to access all registers.
277 virtual uint64_t readIntRegFlat(int idx) = 0;
278 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
280 virtual FloatReg readFloatRegFlat(int idx) = 0;
281 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
283 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
284 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
291 * ProxyThreadContext class that provides a way to implement a
292 * ThreadContext without having to derive from it. ThreadContext is an
293 * abstract class, so anything that derives from it and uses its
294 * interface will pay the overhead of virtual function calls. This
295 * class is created to enable a user-defined Thread object to be used
296 * wherever ThreadContexts are used, without paying the overhead of
297 * virtual function calls when it is used by itself. See
298 * simple_thread.hh for an example of this.
301 class ProxyThreadContext : public ThreadContext
304 ProxyThreadContext(TC *actual_tc)
305 { actualTC = actual_tc; }
312 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
314 int cpuId() { return actualTC->cpuId(); }
316 int threadId() { return actualTC->threadId(); }
318 void setThreadId(int id) { return actualTC->setThreadId(id); }
320 int contextId() { return actualTC->contextId(); }
322 void setContextId(int id) { actualTC->setContextId(id); }
324 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
326 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
328 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
330 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
332 System *getSystemPtr() { return actualTC->getSystemPtr(); }
334 TheISA::Kernel::Statistics *getKernelStats()
335 { return actualTC->getKernelStats(); }
337 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
339 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
341 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
343 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
345 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
347 Status status() const { return actualTC->status(); }
349 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
351 /// Set the status to Active. Optional delay indicates number of
352 /// cycles to wait before beginning execution.
353 void activate(Cycles delay = Cycles(1))
354 { actualTC->activate(delay); }
356 /// Set the status to Suspended.
357 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
359 /// Set the status to Halted.
360 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
362 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
364 void takeOverFrom(ThreadContext *oldContext)
365 { actualTC->takeOverFrom(oldContext); }
367 void regStats(const std::string &name) { actualTC->regStats(name); }
369 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
371 Tick readLastActivate() { return actualTC->readLastActivate(); }
372 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
374 void profileClear() { return actualTC->profileClear(); }
375 void profileSample() { return actualTC->profileSample(); }
377 // @todo: Do I need this?
378 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
380 void clearArchRegs() { actualTC->clearArchRegs(); }
383 // New accessors for new decoder.
385 uint64_t readIntReg(int reg_idx)
386 { return actualTC->readIntReg(reg_idx); }
388 FloatReg readFloatReg(int reg_idx)
389 { return actualTC->readFloatReg(reg_idx); }
391 FloatRegBits readFloatRegBits(int reg_idx)
392 { return actualTC->readFloatRegBits(reg_idx); }
394 void setIntReg(int reg_idx, uint64_t val)
395 { actualTC->setIntReg(reg_idx, val); }
397 void setFloatReg(int reg_idx, FloatReg val)
398 { actualTC->setFloatReg(reg_idx, val); }
400 void setFloatRegBits(int reg_idx, FloatRegBits val)
401 { actualTC->setFloatRegBits(reg_idx, val); }
403 TheISA::PCState pcState() { return actualTC->pcState(); }
405 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
407 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
409 Addr instAddr() { return actualTC->instAddr(); }
410 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
411 MicroPC microPC() { return actualTC->microPC(); }
413 bool readPredicate() { return actualTC->readPredicate(); }
415 void setPredicate(bool val)
416 { actualTC->setPredicate(val); }
418 MiscReg readMiscRegNoEffect(int misc_reg)
419 { return actualTC->readMiscRegNoEffect(misc_reg); }
421 MiscReg readMiscReg(int misc_reg)
422 { return actualTC->readMiscReg(misc_reg); }
424 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
425 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
427 void setMiscReg(int misc_reg, const MiscReg &val)
428 { return actualTC->setMiscReg(misc_reg, val); }
430 int flattenIntIndex(int reg)
431 { return actualTC->flattenIntIndex(reg); }
433 int flattenFloatIndex(int reg)
434 { return actualTC->flattenFloatIndex(reg); }
436 unsigned readStCondFailures()
437 { return actualTC->readStCondFailures(); }
439 void setStCondFailures(unsigned sc_failures)
440 { actualTC->setStCondFailures(sc_failures); }
443 bool misspeculating() { return actualTC->misspeculating(); }
445 void syscall(int64_t callnum)
446 { actualTC->syscall(callnum); }
448 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
450 uint64_t readIntRegFlat(int idx)
451 { return actualTC->readIntRegFlat(idx); }
453 void setIntRegFlat(int idx, uint64_t val)
454 { actualTC->setIntRegFlat(idx, val); }
456 FloatReg readFloatRegFlat(int idx)
457 { return actualTC->readFloatRegFlat(idx); }
459 void setFloatRegFlat(int idx, FloatReg val)
460 { actualTC->setFloatRegFlat(idx, val); }
462 FloatRegBits readFloatRegBitsFlat(int idx)
463 { return actualTC->readFloatRegBitsFlat(idx); }
465 void setFloatRegBitsFlat(int idx, FloatRegBits val)
466 { actualTC->setFloatRegBitsFlat(idx, val); }
471 * Thread context serialization helpers
473 * These helper functions provide a way to the data in a
474 * ThreadContext. They are provided as separate helper function since
475 * implementing them as members of the ThreadContext interface would
476 * be confusing when the ThreadContext is exported via a proxy.
479 void serialize(ThreadContext &tc, std::ostream &os);
480 void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion);
486 * Copy state between thread contexts in preparation for CPU handover.
488 * @note This method modifies the old thread contexts as well as the
489 * new thread context. The old thread context will have its quiesce
490 * event descheduled if it is scheduled and its status set to halted.
492 * @param new_tc Destination ThreadContext.
493 * @param old_tc Source ThreadContext.
495 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);