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31 #ifndef __CPU_THREAD_CONTEXT_HH__
32 #define __CPU_THREAD_CONTEXT_HH__
34 #include "config/full_system.hh"
35 #include "mem/request.hh"
36 #include "sim/faults.hh"
37 #include "sim/host.hh"
38 #include "sim/serialize.hh"
39 #include "sim/byteswap.hh"
41 // @todo: Figure out a more architecture independent way to obtain the ITB and
46 class EndQuiesceEvent;
48 class TranslatingPort;
58 * ThreadContext is the external interface to all thread state for
59 * anything outside of the CPU. It provides all accessor methods to
60 * state that might be needed by external objects, ranging from
61 * register values to things such as kernel stats. It is an abstract
62 * base class; the CPU can create its own ThreadContext by either
63 * deriving from it, or using the templated ProxyThreadContext.
65 * The ThreadContext is slightly different than the ExecContext. The
66 * ThreadContext provides access to an individual thread's state; an
67 * ExecContext provides ISA access to the CPU (meaning it is
68 * implicitly multithreaded on SMT systems). Additionally the
69 * ThreadState is an abstract class that exactly defines the
70 * interface; the ExecContext is a more implicit interface that must
71 * be implemented so that the ISA can access whatever state it needs.
76 typedef TheISA::RegFile RegFile;
77 typedef TheISA::MachInst MachInst;
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81 typedef TheISA::MiscRegFile MiscRegFile;
82 typedef TheISA::MiscReg MiscReg;
86 /// Initialized but not running yet. All CPUs start in
87 /// this state, but most transition to Active on cycle 1.
88 /// In MP or SMT systems, non-primary contexts will stay
89 /// in this state until a thread is assigned to them.
92 /// Running. Instructions should be executed only when
93 /// the context is in this state.
96 /// Temporarily inactive. Entered while waiting for
97 /// synchronization, etc.
100 /// Permanently shut down. Entered when target executes
101 /// m5exit pseudo-instruction. When all contexts enter
102 /// this state, the simulation will terminate.
106 virtual ~ThreadContext() { };
108 virtual BaseCPU *getCpuPtr() = 0;
110 virtual void setCpuId(int id) = 0;
112 virtual int readCpuId() = 0;
115 virtual System *getSystemPtr() = 0;
117 virtual AlphaITB *getITBPtr() = 0;
119 virtual AlphaDTB * getDTBPtr() = 0;
121 virtual Kernel::Statistics *getKernelStats() = 0;
123 virtual FunctionalPort *getPhysPort() = 0;
125 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
127 virtual void delVirtPort(VirtualPort *vp) = 0;
129 virtual TranslatingPort *getMemPort() = 0;
131 virtual Process *getProcessPtr() = 0;
134 virtual Status status() const = 0;
136 virtual void setStatus(Status new_status) = 0;
138 /// Set the status to Active. Optional delay indicates number of
139 /// cycles to wait before beginning execution.
140 virtual void activate(int delay = 1) = 0;
142 /// Set the status to Suspended.
143 virtual void suspend() = 0;
145 /// Set the status to Unallocated.
146 virtual void deallocate(int delay = 0) = 0;
148 /// Set the status to Halted.
149 virtual void halt() = 0;
152 virtual void dumpFuncProfile() = 0;
155 virtual void takeOverFrom(ThreadContext *old_context) = 0;
157 virtual void regStats(const std::string &name) = 0;
159 virtual void serialize(std::ostream &os) = 0;
160 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
163 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
165 // Not necessarily the best location for these...
166 // Having an extra function just to read these is obnoxious
167 virtual Tick readLastActivate() = 0;
168 virtual Tick readLastSuspend() = 0;
170 virtual void profileClear() = 0;
171 virtual void profileSample() = 0;
174 virtual int getThreadNum() = 0;
176 // Also somewhat obnoxious. Really only used for the TLB fault.
177 // However, may be quite useful in SPARC.
178 virtual TheISA::MachInst getInst() = 0;
180 virtual void copyArchRegs(ThreadContext *tc) = 0;
182 virtual void clearArchRegs() = 0;
185 // New accessors for new decoder.
187 virtual uint64_t readIntReg(int reg_idx) = 0;
189 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
191 virtual FloatReg readFloatReg(int reg_idx) = 0;
193 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
195 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
197 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
199 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
201 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
203 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
207 virtual uint64_t readPC() = 0;
209 virtual void setPC(uint64_t val) = 0;
211 virtual uint64_t readNextPC() = 0;
213 virtual void setNextPC(uint64_t val) = 0;
215 virtual uint64_t readNextNPC() = 0;
217 virtual void setNextNPC(uint64_t val) = 0;
219 virtual MiscReg readMiscReg(int misc_reg) = 0;
221 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
223 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
225 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
227 // Also not necessarily the best location for these two. Hopefully will go
228 // away once we decide upon where st cond failures goes.
229 virtual unsigned readStCondFailures() = 0;
231 virtual void setStCondFailures(unsigned sc_failures) = 0;
234 virtual bool inPalMode() = 0;
237 // Only really makes sense for old CPU model. Still could be useful though.
238 virtual bool misspeculating() = 0;
241 virtual IntReg getSyscallArg(int i) = 0;
243 // used to shift args for indirect syscall
244 virtual void setSyscallArg(int i, IntReg val) = 0;
246 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
248 // Same with st cond failures.
249 virtual Counter readFuncExeInst() = 0;
251 // This function exits the thread context in the CPU and returns
252 // 1 if the CPU has no more active threads (meaning it's OK to exit);
253 // Used in syscall-emulation mode when a thread calls the exit syscall.
254 virtual int exit() { return 1; };
257 virtual void changeRegFileContext(RegFile::ContextParam param,
258 RegFile::ContextVal val) = 0;
262 * ProxyThreadContext class that provides a way to implement a
263 * ThreadContext without having to derive from it. ThreadContext is an
264 * abstract class, so anything that derives from it and uses its
265 * interface will pay the overhead of virtual function calls. This
266 * class is created to enable a user-defined Thread object to be used
267 * wherever ThreadContexts are used, without paying the overhead of
268 * virtual function calls when it is used by itself. See
269 * simple_thread.hh for an example of this.
272 class ProxyThreadContext : public ThreadContext
275 ProxyThreadContext(TC *actual_tc)
276 { actualTC = actual_tc; }
283 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
285 void setCpuId(int id) { actualTC->setCpuId(id); }
287 int readCpuId() { return actualTC->readCpuId(); }
290 System *getSystemPtr() { return actualTC->getSystemPtr(); }
292 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
294 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
296 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
298 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
300 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
302 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
304 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
306 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
309 Status status() const { return actualTC->status(); }
311 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
313 /// Set the status to Active. Optional delay indicates number of
314 /// cycles to wait before beginning execution.
315 void activate(int delay = 1) { actualTC->activate(delay); }
317 /// Set the status to Suspended.
318 void suspend() { actualTC->suspend(); }
320 /// Set the status to Unallocated.
321 void deallocate(int delay = 0) { actualTC->deallocate(); }
323 /// Set the status to Halted.
324 void halt() { actualTC->halt(); }
327 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
330 void takeOverFrom(ThreadContext *oldContext)
331 { actualTC->takeOverFrom(oldContext); }
333 void regStats(const std::string &name) { actualTC->regStats(name); }
335 void serialize(std::ostream &os) { actualTC->serialize(os); }
336 void unserialize(Checkpoint *cp, const std::string §ion)
337 { actualTC->unserialize(cp, section); }
340 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
342 Tick readLastActivate() { return actualTC->readLastActivate(); }
343 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
345 void profileClear() { return actualTC->profileClear(); }
346 void profileSample() { return actualTC->profileSample(); }
349 int getThreadNum() { return actualTC->getThreadNum(); }
351 // @todo: Do I need this?
352 MachInst getInst() { return actualTC->getInst(); }
354 // @todo: Do I need this?
355 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
357 void clearArchRegs() { actualTC->clearArchRegs(); }
360 // New accessors for new decoder.
362 uint64_t readIntReg(int reg_idx)
363 { return actualTC->readIntReg(reg_idx); }
365 FloatReg readFloatReg(int reg_idx, int width)
366 { return actualTC->readFloatReg(reg_idx, width); }
368 FloatReg readFloatReg(int reg_idx)
369 { return actualTC->readFloatReg(reg_idx); }
371 FloatRegBits readFloatRegBits(int reg_idx, int width)
372 { return actualTC->readFloatRegBits(reg_idx, width); }
374 FloatRegBits readFloatRegBits(int reg_idx)
375 { return actualTC->readFloatRegBits(reg_idx); }
377 void setIntReg(int reg_idx, uint64_t val)
378 { actualTC->setIntReg(reg_idx, val); }
380 void setFloatReg(int reg_idx, FloatReg val, int width)
381 { actualTC->setFloatReg(reg_idx, val, width); }
383 void setFloatReg(int reg_idx, FloatReg val)
384 { actualTC->setFloatReg(reg_idx, val); }
386 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
387 { actualTC->setFloatRegBits(reg_idx, val, width); }
389 void setFloatRegBits(int reg_idx, FloatRegBits val)
390 { actualTC->setFloatRegBits(reg_idx, val); }
392 uint64_t readPC() { return actualTC->readPC(); }
394 void setPC(uint64_t val) { actualTC->setPC(val); }
396 uint64_t readNextPC() { return actualTC->readNextPC(); }
398 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
400 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
402 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
404 MiscReg readMiscReg(int misc_reg)
405 { return actualTC->readMiscReg(misc_reg); }
407 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
408 { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
410 Fault setMiscReg(int misc_reg, const MiscReg &val)
411 { return actualTC->setMiscReg(misc_reg, val); }
413 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
414 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
416 unsigned readStCondFailures()
417 { return actualTC->readStCondFailures(); }
419 void setStCondFailures(unsigned sc_failures)
420 { actualTC->setStCondFailures(sc_failures); }
422 bool inPalMode() { return actualTC->inPalMode(); }
426 bool misspeculating() { return actualTC->misspeculating(); }
429 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
431 // used to shift args for indirect syscall
432 void setSyscallArg(int i, IntReg val)
433 { actualTC->setSyscallArg(i, val); }
435 void setSyscallReturn(SyscallReturn return_value)
436 { actualTC->setSyscallReturn(return_value); }
438 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
441 void changeRegFileContext(RegFile::ContextParam param,
442 RegFile::ContextVal val)
444 actualTC->changeRegFileContext(param, val);