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43 #ifndef __CPU_THREAD_CONTEXT_HH__
44 #define __CPU_THREAD_CONTEXT_HH__
49 #include "arch/registers.hh"
50 #include "arch/types.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
54 // @todo: Figure out a more architecture independent way to obtain the ITB and
64 class EndQuiesceEvent;
65 class SETranslatingPortProxy;
66 class FSTranslatingPortProxy;
77 * ThreadContext is the external interface to all thread state for
78 * anything outside of the CPU. It provides all accessor methods to
79 * state that might be needed by external objects, ranging from
80 * register values to things such as kernel stats. It is an abstract
81 * base class; the CPU can create its own ThreadContext by either
82 * deriving from it, or using the templated ProxyThreadContext.
84 * The ThreadContext is slightly different than the ExecContext. The
85 * ThreadContext provides access to an individual thread's state; an
86 * ExecContext provides ISA access to the CPU (meaning it is
87 * implicitly multithreaded on SMT systems). Additionally the
88 * ThreadState is an abstract class that exactly defines the
89 * interface; the ExecContext is a more implicit interface that must
90 * be implemented so that the ISA can access whatever state it needs.
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::IntReg IntReg;
97 typedef TheISA::FloatReg FloatReg;
98 typedef TheISA::FloatRegBits FloatRegBits;
99 typedef TheISA::MiscReg MiscReg;
104 /// Running. Instructions should be executed only when
105 /// the context is in this state.
108 /// Temporarily inactive. Entered while waiting for
109 /// synchronization, etc.
112 /// Permanently shut down. Entered when target executes
113 /// m5exit pseudo-instruction. When all contexts enter
114 /// this state, the simulation will terminate.
118 virtual ~ThreadContext() { };
120 virtual BaseCPU *getCpuPtr() = 0;
122 virtual int cpuId() = 0;
124 virtual int threadId() = 0;
126 virtual void setThreadId(int id) = 0;
128 virtual int contextId() = 0;
130 virtual void setContextId(int id) = 0;
132 virtual TheISA::TLB *getITBPtr() = 0;
134 virtual TheISA::TLB *getDTBPtr() = 0;
136 virtual CheckerCPU *getCheckerCpuPtr() = 0;
138 virtual TheISA::Decoder *getDecoderPtr() = 0;
140 virtual System *getSystemPtr() = 0;
142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
144 virtual PortProxy &getPhysProxy() = 0;
146 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
149 * Initialise the physical and virtual port proxies and tie them to
150 * the data port of the CPU.
152 * tc ThreadContext for the virtual-to-physical translation
154 virtual void initMemProxies(ThreadContext *tc) = 0;
156 virtual SETranslatingPortProxy &getMemProxy() = 0;
158 virtual Process *getProcessPtr() = 0;
160 virtual Status status() const = 0;
162 virtual void setStatus(Status new_status) = 0;
164 /// Set the status to Active. Optional delay indicates number of
165 /// cycles to wait before beginning execution.
166 virtual void activate(Cycles delay = Cycles(1)) = 0;
168 /// Set the status to Suspended.
169 virtual void suspend(Cycles delay = Cycles(0)) = 0;
171 /// Set the status to Halted.
172 virtual void halt(Cycles delay = Cycles(0)) = 0;
174 virtual void dumpFuncProfile() = 0;
176 virtual void takeOverFrom(ThreadContext *old_context) = 0;
178 virtual void regStats(const std::string &name) = 0;
180 virtual void serialize(std::ostream &os) = 0;
181 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
183 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
185 // Not necessarily the best location for these...
186 // Having an extra function just to read these is obnoxious
187 virtual Tick readLastActivate() = 0;
188 virtual Tick readLastSuspend() = 0;
190 virtual void profileClear() = 0;
191 virtual void profileSample() = 0;
193 virtual void copyArchRegs(ThreadContext *tc) = 0;
195 virtual void clearArchRegs() = 0;
198 // New accessors for new decoder.
200 virtual uint64_t readIntReg(int reg_idx) = 0;
202 virtual FloatReg readFloatReg(int reg_idx) = 0;
204 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
206 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
208 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
210 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
212 virtual TheISA::PCState pcState() = 0;
214 virtual void pcState(const TheISA::PCState &val) = 0;
216 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
218 virtual Addr instAddr() = 0;
220 virtual Addr nextInstAddr() = 0;
222 virtual MicroPC microPC() = 0;
224 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
226 virtual MiscReg readMiscReg(int misc_reg) = 0;
228 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
230 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
232 virtual int flattenIntIndex(int reg) = 0;
233 virtual int flattenFloatIndex(int reg) = 0;
236 readRegOtherThread(int misc_reg, ThreadID tid)
242 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
246 // Also not necessarily the best location for these two. Hopefully will go
247 // away once we decide upon where st cond failures goes.
248 virtual unsigned readStCondFailures() = 0;
250 virtual void setStCondFailures(unsigned sc_failures) = 0;
252 // Only really makes sense for old CPU model. Still could be useful though.
253 virtual bool misspeculating() = 0;
255 // Same with st cond failures.
256 virtual Counter readFuncExeInst() = 0;
258 virtual void syscall(int64_t callnum) = 0;
260 // This function exits the thread context in the CPU and returns
261 // 1 if the CPU has no more active threads (meaning it's OK to exit);
262 // Used in syscall-emulation mode when a thread calls the exit syscall.
263 virtual int exit() { return 1; };
265 /** function to compare two thread contexts (for debugging) */
266 static void compare(ThreadContext *one, ThreadContext *two);
270 * ProxyThreadContext class that provides a way to implement a
271 * ThreadContext without having to derive from it. ThreadContext is an
272 * abstract class, so anything that derives from it and uses its
273 * interface will pay the overhead of virtual function calls. This
274 * class is created to enable a user-defined Thread object to be used
275 * wherever ThreadContexts are used, without paying the overhead of
276 * virtual function calls when it is used by itself. See
277 * simple_thread.hh for an example of this.
280 class ProxyThreadContext : public ThreadContext
283 ProxyThreadContext(TC *actual_tc)
284 { actualTC = actual_tc; }
291 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
293 int cpuId() { return actualTC->cpuId(); }
295 int threadId() { return actualTC->threadId(); }
297 void setThreadId(int id) { return actualTC->setThreadId(id); }
299 int contextId() { return actualTC->contextId(); }
301 void setContextId(int id) { actualTC->setContextId(id); }
303 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
305 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
307 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
309 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
311 System *getSystemPtr() { return actualTC->getSystemPtr(); }
313 TheISA::Kernel::Statistics *getKernelStats()
314 { return actualTC->getKernelStats(); }
316 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
318 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
320 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
322 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
324 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
326 Status status() const { return actualTC->status(); }
328 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
330 /// Set the status to Active. Optional delay indicates number of
331 /// cycles to wait before beginning execution.
332 void activate(Cycles delay = Cycles(1))
333 { actualTC->activate(delay); }
335 /// Set the status to Suspended.
336 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
338 /// Set the status to Halted.
339 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
341 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
343 void takeOverFrom(ThreadContext *oldContext)
344 { actualTC->takeOverFrom(oldContext); }
346 void regStats(const std::string &name) { actualTC->regStats(name); }
348 void serialize(std::ostream &os) { actualTC->serialize(os); }
349 void unserialize(Checkpoint *cp, const std::string §ion)
350 { actualTC->unserialize(cp, section); }
352 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
354 Tick readLastActivate() { return actualTC->readLastActivate(); }
355 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
357 void profileClear() { return actualTC->profileClear(); }
358 void profileSample() { return actualTC->profileSample(); }
360 // @todo: Do I need this?
361 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
363 void clearArchRegs() { actualTC->clearArchRegs(); }
366 // New accessors for new decoder.
368 uint64_t readIntReg(int reg_idx)
369 { return actualTC->readIntReg(reg_idx); }
371 FloatReg readFloatReg(int reg_idx)
372 { return actualTC->readFloatReg(reg_idx); }
374 FloatRegBits readFloatRegBits(int reg_idx)
375 { return actualTC->readFloatRegBits(reg_idx); }
377 void setIntReg(int reg_idx, uint64_t val)
378 { actualTC->setIntReg(reg_idx, val); }
380 void setFloatReg(int reg_idx, FloatReg val)
381 { actualTC->setFloatReg(reg_idx, val); }
383 void setFloatRegBits(int reg_idx, FloatRegBits val)
384 { actualTC->setFloatRegBits(reg_idx, val); }
386 TheISA::PCState pcState() { return actualTC->pcState(); }
388 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
390 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
392 Addr instAddr() { return actualTC->instAddr(); }
393 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
394 MicroPC microPC() { return actualTC->microPC(); }
396 bool readPredicate() { return actualTC->readPredicate(); }
398 void setPredicate(bool val)
399 { actualTC->setPredicate(val); }
401 MiscReg readMiscRegNoEffect(int misc_reg)
402 { return actualTC->readMiscRegNoEffect(misc_reg); }
404 MiscReg readMiscReg(int misc_reg)
405 { return actualTC->readMiscReg(misc_reg); }
407 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
408 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
410 void setMiscReg(int misc_reg, const MiscReg &val)
411 { return actualTC->setMiscReg(misc_reg, val); }
413 int flattenIntIndex(int reg)
414 { return actualTC->flattenIntIndex(reg); }
416 int flattenFloatIndex(int reg)
417 { return actualTC->flattenFloatIndex(reg); }
419 unsigned readStCondFailures()
420 { return actualTC->readStCondFailures(); }
422 void setStCondFailures(unsigned sc_failures)
423 { actualTC->setStCondFailures(sc_failures); }
426 bool misspeculating() { return actualTC->misspeculating(); }
428 void syscall(int64_t callnum)
429 { actualTC->syscall(callnum); }
431 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }