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44 #ifndef __CPU_THREAD_CONTEXT_HH__
45 #define __CPU_THREAD_CONTEXT_HH__
50 #include "arch/registers.hh"
51 #include "arch/types.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/reg_class.hh"
56 // @todo: Figure out a more architecture independent way to obtain the ITB and
66 class EndQuiesceEvent;
67 class SETranslatingPortProxy;
68 class FSTranslatingPortProxy;
79 * ThreadContext is the external interface to all thread state for
80 * anything outside of the CPU. It provides all accessor methods to
81 * state that might be needed by external objects, ranging from
82 * register values to things such as kernel stats. It is an abstract
83 * base class; the CPU can create its own ThreadContext by either
84 * deriving from it, or using the templated ProxyThreadContext.
86 * The ThreadContext is slightly different than the ExecContext. The
87 * ThreadContext provides access to an individual thread's state; an
88 * ExecContext provides ISA access to the CPU (meaning it is
89 * implicitly multithreaded on SMT systems). Additionally the
90 * ThreadState is an abstract class that exactly defines the
91 * interface; the ExecContext is a more implicit interface that must
92 * be implemented so that the ISA can access whatever state it needs.
97 typedef TheISA::MachInst MachInst;
98 typedef TheISA::IntReg IntReg;
99 typedef TheISA::FloatReg FloatReg;
100 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef TheISA::CCReg CCReg;
102 typedef TheISA::MiscReg MiscReg;
103 using VecRegContainer = TheISA::VecRegContainer;
104 using VecElem = TheISA::VecElem;
109 /// Running. Instructions should be executed only when
110 /// the context is in this state.
113 /// Temporarily inactive. Entered while waiting for
114 /// synchronization, etc.
117 /// Permanently shut down. Entered when target executes
118 /// m5exit pseudo-instruction. When all contexts enter
119 /// this state, the simulation will terminate.
123 virtual ~ThreadContext() { };
125 virtual BaseCPU *getCpuPtr() = 0;
127 virtual int cpuId() const = 0;
129 virtual uint32_t socketId() const = 0;
131 virtual int threadId() const = 0;
133 virtual void setThreadId(int id) = 0;
135 virtual int contextId() const = 0;
137 virtual void setContextId(int id) = 0;
139 virtual TheISA::TLB *getITBPtr() = 0;
141 virtual TheISA::TLB *getDTBPtr() = 0;
143 virtual CheckerCPU *getCheckerCpuPtr() = 0;
145 virtual TheISA::Decoder *getDecoderPtr() = 0;
147 virtual System *getSystemPtr() = 0;
149 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
151 virtual PortProxy &getPhysProxy() = 0;
153 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
156 * Initialise the physical and virtual port proxies and tie them to
157 * the data port of the CPU.
159 * tc ThreadContext for the virtual-to-physical translation
161 virtual void initMemProxies(ThreadContext *tc) = 0;
163 virtual SETranslatingPortProxy &getMemProxy() = 0;
165 virtual Process *getProcessPtr() = 0;
167 virtual void setProcessPtr(Process *p) = 0;
169 virtual Status status() const = 0;
171 virtual void setStatus(Status new_status) = 0;
173 /// Set the status to Active.
174 virtual void activate() = 0;
176 /// Set the status to Suspended.
177 virtual void suspend() = 0;
179 /// Set the status to Halted.
180 virtual void halt() = 0;
182 /// Quiesce thread context
185 /// Quiesce, suspend, and schedule activate at resume
186 void quiesceTick(Tick resume);
188 virtual void dumpFuncProfile() = 0;
190 virtual void takeOverFrom(ThreadContext *old_context) = 0;
192 virtual void regStats(const std::string &name) = 0;
194 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
196 // Not necessarily the best location for these...
197 // Having an extra function just to read these is obnoxious
198 virtual Tick readLastActivate() = 0;
199 virtual Tick readLastSuspend() = 0;
201 virtual void profileClear() = 0;
202 virtual void profileSample() = 0;
204 virtual void copyArchRegs(ThreadContext *tc) = 0;
206 virtual void clearArchRegs() = 0;
209 // New accessors for new decoder.
211 virtual uint64_t readIntReg(int reg_idx) = 0;
213 virtual FloatReg readFloatReg(int reg_idx) = 0;
215 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
220 /** Vector Register Lane Interfaces. */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
251 virtual CCReg readCCReg(int reg_idx) = 0;
253 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
255 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
257 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
259 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
261 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
263 virtual void setCCReg(int reg_idx, CCReg val) = 0;
265 virtual TheISA::PCState pcState() = 0;
267 virtual void pcState(const TheISA::PCState &val) = 0;
272 TheISA::PCState pc_state = pcState();
273 pc_state.setNPC(val);
277 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
279 virtual Addr instAddr() = 0;
281 virtual Addr nextInstAddr() = 0;
283 virtual MicroPC microPC() = 0;
285 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
287 virtual MiscReg readMiscReg(int misc_reg) = 0;
289 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
291 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
293 virtual RegId flattenRegId(const RegId& regId) const = 0;
296 readRegOtherThread(const RegId& misc_reg, ThreadID tid)
302 setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
306 // Also not necessarily the best location for these two. Hopefully will go
307 // away once we decide upon where st cond failures goes.
308 virtual unsigned readStCondFailures() = 0;
310 virtual void setStCondFailures(unsigned sc_failures) = 0;
312 // Same with st cond failures.
313 virtual Counter readFuncExeInst() = 0;
315 virtual void syscall(int64_t callnum, Fault *fault) = 0;
317 // This function exits the thread context in the CPU and returns
318 // 1 if the CPU has no more active threads (meaning it's OK to exit);
319 // Used in syscall-emulation mode when a thread calls the exit syscall.
320 virtual int exit() { return 1; };
322 /** function to compare two thread contexts (for debugging) */
323 static void compare(ThreadContext *one, ThreadContext *two);
327 * Flat register interfaces
329 * Some architectures have different registers visible in
330 * different modes. Such architectures "flatten" a register (see
331 * flattenRegId()) to map it into the
332 * gem5 register file. This interface provides a flat interface to
333 * the underlying register file, which allows for example
334 * serialization code to access all registers.
337 virtual uint64_t readIntRegFlat(int idx) = 0;
338 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
340 virtual FloatReg readFloatRegFlat(int idx) = 0;
341 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
343 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
344 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
346 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
347 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
348 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0;
350 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
351 const ElemIndex& elemIdx) const = 0;
352 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
353 const VecElem& val) = 0;
355 virtual CCReg readCCRegFlat(int idx) = 0;
356 virtual void setCCRegFlat(int idx, CCReg val) = 0;
362 * ProxyThreadContext class that provides a way to implement a
363 * ThreadContext without having to derive from it. ThreadContext is an
364 * abstract class, so anything that derives from it and uses its
365 * interface will pay the overhead of virtual function calls. This
366 * class is created to enable a user-defined Thread object to be used
367 * wherever ThreadContexts are used, without paying the overhead of
368 * virtual function calls when it is used by itself. See
369 * simple_thread.hh for an example of this.
372 class ProxyThreadContext : public ThreadContext
375 ProxyThreadContext(TC *actual_tc)
376 { actualTC = actual_tc; }
383 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
385 int cpuId() const { return actualTC->cpuId(); }
387 uint32_t socketId() const { return actualTC->socketId(); }
389 int threadId() const { return actualTC->threadId(); }
391 void setThreadId(int id) { actualTC->setThreadId(id); }
393 int contextId() const { return actualTC->contextId(); }
395 void setContextId(int id) { actualTC->setContextId(id); }
397 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
399 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
401 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
403 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
405 System *getSystemPtr() { return actualTC->getSystemPtr(); }
407 TheISA::Kernel::Statistics *getKernelStats()
408 { return actualTC->getKernelStats(); }
410 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
412 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
414 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
416 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
418 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
420 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
422 Status status() const { return actualTC->status(); }
424 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
426 /// Set the status to Active.
427 void activate() { actualTC->activate(); }
429 /// Set the status to Suspended.
430 void suspend() { actualTC->suspend(); }
432 /// Set the status to Halted.
433 void halt() { actualTC->halt(); }
435 /// Quiesce thread context
436 void quiesce() { actualTC->quiesce(); }
438 /// Quiesce, suspend, and schedule activate at resume
439 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
441 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
443 void takeOverFrom(ThreadContext *oldContext)
444 { actualTC->takeOverFrom(oldContext); }
446 void regStats(const std::string &name) { actualTC->regStats(name); }
448 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
450 Tick readLastActivate() { return actualTC->readLastActivate(); }
451 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
453 void profileClear() { return actualTC->profileClear(); }
454 void profileSample() { return actualTC->profileSample(); }
456 // @todo: Do I need this?
457 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
459 void clearArchRegs() { actualTC->clearArchRegs(); }
462 // New accessors for new decoder.
464 uint64_t readIntReg(int reg_idx)
465 { return actualTC->readIntReg(reg_idx); }
467 FloatReg readFloatReg(int reg_idx)
468 { return actualTC->readFloatReg(reg_idx); }
470 FloatRegBits readFloatRegBits(int reg_idx)
471 { return actualTC->readFloatRegBits(reg_idx); }
473 const VecRegContainer& readVecReg(const RegId& reg) const
474 { return actualTC->readVecReg(reg); }
476 VecRegContainer& getWritableVecReg(const RegId& reg)
477 { return actualTC->getWritableVecReg(reg); }
479 /** Vector Register Lane Interfaces. */
481 /** Reads source vector 8bit operand. */
483 readVec8BitLaneReg(const RegId& reg) const
484 { return actualTC->readVec8BitLaneReg(reg); }
486 /** Reads source vector 16bit operand. */
488 readVec16BitLaneReg(const RegId& reg) const
489 { return actualTC->readVec16BitLaneReg(reg); }
491 /** Reads source vector 32bit operand. */
493 readVec32BitLaneReg(const RegId& reg) const
494 { return actualTC->readVec32BitLaneReg(reg); }
496 /** Reads source vector 64bit operand. */
498 readVec64BitLaneReg(const RegId& reg) const
499 { return actualTC->readVec64BitLaneReg(reg); }
501 /** Write a lane of the destination vector register. */
502 virtual void setVecLane(const RegId& reg,
503 const LaneData<LaneSize::Byte>& val)
504 { return actualTC->setVecLane(reg, val); }
505 virtual void setVecLane(const RegId& reg,
506 const LaneData<LaneSize::TwoByte>& val)
507 { return actualTC->setVecLane(reg, val); }
508 virtual void setVecLane(const RegId& reg,
509 const LaneData<LaneSize::FourByte>& val)
510 { return actualTC->setVecLane(reg, val); }
511 virtual void setVecLane(const RegId& reg,
512 const LaneData<LaneSize::EightByte>& val)
513 { return actualTC->setVecLane(reg, val); }
516 const VecElem& readVecElem(const RegId& reg) const
517 { return actualTC->readVecElem(reg); }
519 CCReg readCCReg(int reg_idx)
520 { return actualTC->readCCReg(reg_idx); }
522 void setIntReg(int reg_idx, uint64_t val)
523 { actualTC->setIntReg(reg_idx, val); }
525 void setFloatReg(int reg_idx, FloatReg val)
526 { actualTC->setFloatReg(reg_idx, val); }
528 void setFloatRegBits(int reg_idx, FloatRegBits val)
529 { actualTC->setFloatRegBits(reg_idx, val); }
531 void setVecReg(const RegId& reg, const VecRegContainer& val)
532 { actualTC->setVecReg(reg, val); }
534 void setVecElem(const RegId& reg, const VecElem& val)
535 { actualTC->setVecElem(reg, val); }
537 void setCCReg(int reg_idx, CCReg val)
538 { actualTC->setCCReg(reg_idx, val); }
540 TheISA::PCState pcState() { return actualTC->pcState(); }
542 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
544 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
546 Addr instAddr() { return actualTC->instAddr(); }
547 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
548 MicroPC microPC() { return actualTC->microPC(); }
550 bool readPredicate() { return actualTC->readPredicate(); }
552 void setPredicate(bool val)
553 { actualTC->setPredicate(val); }
555 MiscReg readMiscRegNoEffect(int misc_reg) const
556 { return actualTC->readMiscRegNoEffect(misc_reg); }
558 MiscReg readMiscReg(int misc_reg)
559 { return actualTC->readMiscReg(misc_reg); }
561 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
562 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
564 void setMiscReg(int misc_reg, const MiscReg &val)
565 { return actualTC->setMiscReg(misc_reg, val); }
567 RegId flattenRegId(const RegId& regId) const
568 { return actualTC->flattenRegId(regId); }
570 unsigned readStCondFailures()
571 { return actualTC->readStCondFailures(); }
573 void setStCondFailures(unsigned sc_failures)
574 { actualTC->setStCondFailures(sc_failures); }
576 void syscall(int64_t callnum, Fault *fault)
577 { actualTC->syscall(callnum, fault); }
579 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
581 uint64_t readIntRegFlat(int idx)
582 { return actualTC->readIntRegFlat(idx); }
584 void setIntRegFlat(int idx, uint64_t val)
585 { actualTC->setIntRegFlat(idx, val); }
587 FloatReg readFloatRegFlat(int idx)
588 { return actualTC->readFloatRegFlat(idx); }
590 void setFloatRegFlat(int idx, FloatReg val)
591 { actualTC->setFloatRegFlat(idx, val); }
593 FloatRegBits readFloatRegBitsFlat(int idx)
594 { return actualTC->readFloatRegBitsFlat(idx); }
596 void setFloatRegBitsFlat(int idx, FloatRegBits val)
597 { actualTC->setFloatRegBitsFlat(idx, val); }
599 const VecRegContainer& readVecRegFlat(int id) const
600 { return actualTC->readVecRegFlat(id); }
602 VecRegContainer& getWritableVecRegFlat(int id)
603 { return actualTC->getWritableVecRegFlat(id); }
605 void setVecRegFlat(int idx, const VecRegContainer& val)
606 { actualTC->setVecRegFlat(idx, val); }
608 const VecElem& readVecElemFlat(const RegIndex& id,
609 const ElemIndex& elemIndex) const
610 { return actualTC->readVecElemFlat(id, elemIndex); }
612 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex,
614 { actualTC->setVecElemFlat(id, elemIndex, val); }
616 CCReg readCCRegFlat(int idx)
617 { return actualTC->readCCRegFlat(idx); }
619 void setCCRegFlat(int idx, CCReg val)
620 { actualTC->setCCRegFlat(idx, val); }
625 * Thread context serialization helpers
627 * These helper functions provide a way to the data in a
628 * ThreadContext. They are provided as separate helper function since
629 * implementing them as members of the ThreadContext interface would
630 * be confusing when the ThreadContext is exported via a proxy.
633 void serialize(ThreadContext &tc, CheckpointOut &cp);
634 void unserialize(ThreadContext &tc, CheckpointIn &cp);
640 * Copy state between thread contexts in preparation for CPU handover.
642 * @note This method modifies the old thread contexts as well as the
643 * new thread context. The old thread context will have its quiesce
644 * event descheduled if it is scheduled and its status set to halted.
646 * @param new_tc Destination ThreadContext.
647 * @param old_tc Source ThreadContext.
649 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);