src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include <iostream>
  35 #include <string>
  36
  37 #include "arch/registers.hh"
  38 #include "arch/types.hh"
  39 #include "base/types.hh"
  40 #include "config/the_isa.hh"
  41
  42 // @todo: Figure out a more architecture independent way to obtain the ITB and
  43 // DTB pointers.
  44 namespace TheISA
  45 {
  46     class TLB;
  47 }
  48 class BaseCPU;
  49 class Checkpoint;
  50 class Decoder;
  51 class EndQuiesceEvent;
  52 class TranslatingPort;
  53 class FunctionalPort;
  54 class VirtualPort;
  55 class Process;
  56 class System;
  57 namespace TheISA {
  58     namespace Kernel {
  59         class Statistics;
  60     };
  61 };
  62
  63 /**
  64  * ThreadContext is the external interface to all thread state for
  65  * anything outside of the CPU. It provides all accessor methods to
  66  * state that might be needed by external objects, ranging from
  67  * register values to things such as kernel stats. It is an abstract
  68  * base class; the CPU can create its own ThreadContext by either
  69  * deriving from it, or using the templated ProxyThreadContext.
  70  *
  71  * The ThreadContext is slightly different than the ExecContext.  The
  72  * ThreadContext provides access to an individual thread's state; an
  73  * ExecContext provides ISA access to the CPU (meaning it is
  74  * implicitly multithreaded on SMT systems).  Additionally the
  75  * ThreadState is an abstract class that exactly defines the
  76  * interface; the ExecContext is a more implicit interface that must
  77  * be implemented so that the ISA can access whatever state it needs.
  78  */
  79 class ThreadContext
  80 {
  81   protected:
  82     typedef TheISA::MachInst MachInst;
  83     typedef TheISA::IntReg IntReg;
  84     typedef TheISA::FloatReg FloatReg;
  85     typedef TheISA::FloatRegBits FloatRegBits;
  86     typedef TheISA::MiscReg MiscReg;
  87   public:
  88
  89     enum Status
  90     {
  91         /// Running.  Instructions should be executed only when
  92         /// the context is in this state.
  93         Active,
  94
  95         /// Temporarily inactive.  Entered while waiting for
  96         /// synchronization, etc.
  97         Suspended,
  98
  99         /// Permanently shut down.  Entered when target executes
 100         /// m5exit pseudo-instruction.  When all contexts enter
 101         /// this state, the simulation will terminate.
 102         Halted
 103     };
 104
 105     virtual ~ThreadContext() { };
 106
 107     virtual BaseCPU *getCpuPtr() = 0;
 108
 109     virtual int cpuId() = 0;
 110
 111     virtual int threadId() = 0;
 112
 113     virtual void setThreadId(int id) = 0;
 114
 115     virtual int contextId() = 0;
 116
 117     virtual void setContextId(int id) = 0;
 118
 119     virtual TheISA::TLB *getITBPtr() = 0;
 120
 121     virtual TheISA::TLB *getDTBPtr() = 0;
 122
 123     virtual Decoder *getDecoderPtr() = 0;
 124
 125     virtual System *getSystemPtr() = 0;
 126
 127     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 128
 129     virtual void connectMemPorts(ThreadContext *tc) = 0;
 130
 131     virtual Process *getProcessPtr() = 0;
 132
 133     virtual TranslatingPort *getMemPort() = 0;
 134
 135     virtual VirtualPort *getVirtPort() = 0;
 136
 137     virtual FunctionalPort *getPhysPort() = 0;
 138
 139     virtual Status status() const = 0;
 140
 141     virtual void setStatus(Status new_status) = 0;
 142
 143     /// Set the status to Active.  Optional delay indicates number of
 144     /// cycles to wait before beginning execution.
 145     virtual void activate(int delay = 1) = 0;
 146
 147     /// Set the status to Suspended.
 148     virtual void suspend(int delay = 0) = 0;
 149
 150     /// Set the status to Halted.
 151     virtual void halt(int delay = 0) = 0;
 152
 153     virtual void dumpFuncProfile() = 0;
 154
 155     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 156
 157     virtual void regStats(const std::string &name) = 0;
 158
 159     virtual void serialize(std::ostream &os) = 0;
 160     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 161
 162     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 163
 164     // Not necessarily the best location for these...
 165     // Having an extra function just to read these is obnoxious
 166     virtual Tick readLastActivate() = 0;
 167     virtual Tick readLastSuspend() = 0;
 168
 169     virtual void profileClear() = 0;
 170     virtual void profileSample() = 0;
 171
 172     virtual void copyArchRegs(ThreadContext *tc) = 0;
 173
 174     virtual void clearArchRegs() = 0;
 175
 176     //
 177     // New accessors for new decoder.
 178     //
 179     virtual uint64_t readIntReg(int reg_idx) = 0;
 180
 181     virtual FloatReg readFloatReg(int reg_idx) = 0;
 182
 183     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 184
 185     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 186
 187     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 188
 189     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 190
 191     virtual TheISA::PCState pcState() = 0;
 192
 193     virtual void pcState(const TheISA::PCState &val) = 0;
 194
 195     virtual Addr instAddr() = 0;
 196
 197     virtual Addr nextInstAddr() = 0;
 198
 199     virtual MicroPC microPC() = 0;
 200
 201     virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 202
 203     virtual MiscReg readMiscReg(int misc_reg) = 0;
 204
 205     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 206
 207     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 208
 209     virtual int flattenIntIndex(int reg) = 0;
 210     virtual int flattenFloatIndex(int reg) = 0;
 211
 212     virtual uint64_t
 213     readRegOtherThread(int misc_reg, ThreadID tid)
 214     {
 215         return 0;
 216     }
 217
 218     virtual void
 219     setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
 220     {
 221     }
 222
 223     // Also not necessarily the best location for these two.  Hopefully will go
 224     // away once we decide upon where st cond failures goes.
 225     virtual unsigned readStCondFailures() = 0;
 226
 227     virtual void setStCondFailures(unsigned sc_failures) = 0;
 228
 229     // Only really makes sense for old CPU model.  Still could be useful though.
 230     virtual bool misspeculating() = 0;
 231
 232     // Same with st cond failures.
 233     virtual Counter readFuncExeInst() = 0;
 234
 235     virtual void syscall(int64_t callnum) = 0;
 236
 237     // This function exits the thread context in the CPU and returns
 238     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 239     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 240     virtual int exit() { return 1; };
 241
 242     /** function to compare two thread contexts (for debugging) */
 243     static void compare(ThreadContext *one, ThreadContext *two);
 244 };
 245
 246 /**
 247  * ProxyThreadContext class that provides a way to implement a
 248  * ThreadContext without having to derive from it. ThreadContext is an
 249  * abstract class, so anything that derives from it and uses its
 250  * interface will pay the overhead of virtual function calls.  This
 251  * class is created to enable a user-defined Thread object to be used
 252  * wherever ThreadContexts are used, without paying the overhead of
 253  * virtual function calls when it is used by itself.  See
 254  * simple_thread.hh for an example of this.
 255  */
 256 template <class TC>
 257 class ProxyThreadContext : public ThreadContext
 258 {
 259   public:
 260     ProxyThreadContext(TC *actual_tc)
 261     { actualTC = actual_tc; }
 262
 263   private:
 264     TC *actualTC;
 265
 266   public:
 267
 268     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 269
 270     int cpuId() { return actualTC->cpuId(); }
 271
 272     int threadId() { return actualTC->threadId(); }
 273
 274     void setThreadId(int id) { return actualTC->setThreadId(id); }
 275
 276     int contextId() { return actualTC->contextId(); }
 277
 278     void setContextId(int id) { actualTC->setContextId(id); }
 279
 280     TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 281
 282     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 283
 284     Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 285
 286     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 287
 288     TheISA::Kernel::Statistics *getKernelStats()
 289     { return actualTC->getKernelStats(); }
 290
 291     void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 292
 293     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 294
 295     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 296
 297     VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
 298
 299     FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 300
 301     Status status() const { return actualTC->status(); }
 302
 303     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 304
 305     /// Set the status to Active.  Optional delay indicates number of
 306     /// cycles to wait before beginning execution.
 307     void activate(int delay = 1) { actualTC->activate(delay); }
 308
 309     /// Set the status to Suspended.
 310     void suspend(int delay = 0) { actualTC->suspend(); }
 311
 312     /// Set the status to Halted.
 313     void halt(int delay = 0) { actualTC->halt(); }
 314
 315     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 316
 317     void takeOverFrom(ThreadContext *oldContext)
 318     { actualTC->takeOverFrom(oldContext); }
 319
 320     void regStats(const std::string &name) { actualTC->regStats(name); }
 321
 322     void serialize(std::ostream &os) { actualTC->serialize(os); }
 323     void unserialize(Checkpoint *cp, const std::string &section)
 324     { actualTC->unserialize(cp, section); }
 325
 326     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 327
 328     Tick readLastActivate() { return actualTC->readLastActivate(); }
 329     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 330
 331     void profileClear() { return actualTC->profileClear(); }
 332     void profileSample() { return actualTC->profileSample(); }
 333
 334     // @todo: Do I need this?
 335     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 336
 337     void clearArchRegs() { actualTC->clearArchRegs(); }
 338
 339     //
 340     // New accessors for new decoder.
 341     //
 342     uint64_t readIntReg(int reg_idx)
 343     { return actualTC->readIntReg(reg_idx); }
 344
 345     FloatReg readFloatReg(int reg_idx)
 346     { return actualTC->readFloatReg(reg_idx); }
 347
 348     FloatRegBits readFloatRegBits(int reg_idx)
 349     { return actualTC->readFloatRegBits(reg_idx); }
 350
 351     void setIntReg(int reg_idx, uint64_t val)
 352     { actualTC->setIntReg(reg_idx, val); }
 353
 354     void setFloatReg(int reg_idx, FloatReg val)
 355     { actualTC->setFloatReg(reg_idx, val); }
 356
 357     void setFloatRegBits(int reg_idx, FloatRegBits val)
 358     { actualTC->setFloatRegBits(reg_idx, val); }
 359
 360     TheISA::PCState pcState() { return actualTC->pcState(); }
 361
 362     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 363
 364     Addr instAddr() { return actualTC->instAddr(); }
 365     Addr nextInstAddr() { return actualTC->nextInstAddr(); }
 366     MicroPC microPC() { return actualTC->microPC(); }
 367
 368     bool readPredicate() { return actualTC->readPredicate(); }
 369
 370     void setPredicate(bool val)
 371     { actualTC->setPredicate(val); }
 372
 373     MiscReg readMiscRegNoEffect(int misc_reg)
 374     { return actualTC->readMiscRegNoEffect(misc_reg); }
 375
 376     MiscReg readMiscReg(int misc_reg)
 377     { return actualTC->readMiscReg(misc_reg); }
 378
 379     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 380     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 381
 382     void setMiscReg(int misc_reg, const MiscReg &val)
 383     { return actualTC->setMiscReg(misc_reg, val); }
 384
 385     int flattenIntIndex(int reg)
 386     { return actualTC->flattenIntIndex(reg); }
 387
 388     int flattenFloatIndex(int reg)
 389     { return actualTC->flattenFloatIndex(reg); }
 390
 391     unsigned readStCondFailures()
 392     { return actualTC->readStCondFailures(); }
 393
 394     void setStCondFailures(unsigned sc_failures)
 395     { actualTC->setStCondFailures(sc_failures); }
 396
 397     // @todo: Fix this!
 398     bool misspeculating() { return actualTC->misspeculating(); }
 399
 400     void syscall(int64_t callnum)
 401     { actualTC->syscall(callnum); }
 402
 403     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 404 };
 405
 406 #endif