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31 #ifndef __CPU_THREAD_CONTEXT_HH__
32 #define __CPU_THREAD_CONTEXT_HH__
34 #include "arch/regfile.hh"
35 #include "arch/syscallreturn.hh"
36 #include "arch/types.hh"
37 #include "config/full_system.hh"
38 #include "mem/request.hh"
39 #include "sim/faults.hh"
40 #include "sim/host.hh"
41 #include "sim/serialize.hh"
42 #include "sim/byteswap.hh"
44 // @todo: Figure out a more architecture independent way to obtain the ITB and
52 class EndQuiesceEvent;
54 class TranslatingPort;
66 * ThreadContext is the external interface to all thread state for
67 * anything outside of the CPU. It provides all accessor methods to
68 * state that might be needed by external objects, ranging from
69 * register values to things such as kernel stats. It is an abstract
70 * base class; the CPU can create its own ThreadContext by either
71 * deriving from it, or using the templated ProxyThreadContext.
73 * The ThreadContext is slightly different than the ExecContext. The
74 * ThreadContext provides access to an individual thread's state; an
75 * ExecContext provides ISA access to the CPU (meaning it is
76 * implicitly multithreaded on SMT systems). Additionally the
77 * ThreadState is an abstract class that exactly defines the
78 * interface; the ExecContext is a more implicit interface that must
79 * be implemented so that the ISA can access whatever state it needs.
84 typedef TheISA::RegFile RegFile;
85 typedef TheISA::MachInst MachInst;
86 typedef TheISA::IntReg IntReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::MiscRegFile MiscRegFile;
90 typedef TheISA::MiscReg MiscReg;
94 /// Initialized but not running yet. All CPUs start in
95 /// this state, but most transition to Active on cycle 1.
96 /// In MP or SMT systems, non-primary contexts will stay
97 /// in this state until a thread is assigned to them.
100 /// Running. Instructions should be executed only when
101 /// the context is in this state.
104 /// Temporarily inactive. Entered while waiting for
105 /// synchronization, etc.
108 /// Permanently shut down. Entered when target executes
109 /// m5exit pseudo-instruction. When all contexts enter
110 /// this state, the simulation will terminate.
114 virtual ~ThreadContext() { };
116 virtual BaseCPU *getCpuPtr() = 0;
118 virtual void setCpuId(int id) = 0;
120 virtual int readCpuId() = 0;
123 virtual System *getSystemPtr() = 0;
125 virtual TheISA::ITB *getITBPtr() = 0;
127 virtual TheISA::DTB *getDTBPtr() = 0;
129 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
131 virtual FunctionalPort *getPhysPort() = 0;
133 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
135 virtual void delVirtPort(VirtualPort *vp) = 0;
137 virtual void connectMemPorts() = 0;
139 virtual TranslatingPort *getMemPort() = 0;
141 virtual Process *getProcessPtr() = 0;
144 virtual Status status() const = 0;
146 virtual void setStatus(Status new_status) = 0;
148 /// Set the status to Active. Optional delay indicates number of
149 /// cycles to wait before beginning execution.
150 virtual void activate(int delay = 1) = 0;
152 /// Set the status to Suspended.
153 virtual void suspend() = 0;
155 /// Set the status to Unallocated.
156 virtual void deallocate(int delay = 0) = 0;
158 /// Set the status to Halted.
159 virtual void halt() = 0;
162 virtual void dumpFuncProfile() = 0;
165 virtual void takeOverFrom(ThreadContext *old_context) = 0;
167 virtual void regStats(const std::string &name) = 0;
169 virtual void serialize(std::ostream &os) = 0;
170 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
173 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
175 // Not necessarily the best location for these...
176 // Having an extra function just to read these is obnoxious
177 virtual Tick readLastActivate() = 0;
178 virtual Tick readLastSuspend() = 0;
180 virtual void profileClear() = 0;
181 virtual void profileSample() = 0;
184 virtual int getThreadNum() = 0;
186 // Also somewhat obnoxious. Really only used for the TLB fault.
187 // However, may be quite useful in SPARC.
188 virtual TheISA::MachInst getInst() = 0;
190 virtual void copyArchRegs(ThreadContext *tc) = 0;
192 virtual void clearArchRegs() = 0;
195 // New accessors for new decoder.
197 virtual uint64_t readIntReg(int reg_idx) = 0;
199 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
201 virtual FloatReg readFloatReg(int reg_idx) = 0;
203 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
205 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
207 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
209 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
211 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
213 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
215 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
217 virtual uint64_t readPC() = 0;
219 virtual void setPC(uint64_t val) = 0;
221 virtual uint64_t readNextPC() = 0;
223 virtual void setNextPC(uint64_t val) = 0;
225 virtual uint64_t readNextNPC() = 0;
227 virtual void setNextNPC(uint64_t val) = 0;
229 virtual MiscReg readMiscReg(int misc_reg) = 0;
231 virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
233 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
235 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
237 // Also not necessarily the best location for these two. Hopefully will go
238 // away once we decide upon where st cond failures goes.
239 virtual unsigned readStCondFailures() = 0;
241 virtual void setStCondFailures(unsigned sc_failures) = 0;
243 // Only really makes sense for old CPU model. Still could be useful though.
244 virtual bool misspeculating() = 0;
247 virtual IntReg getSyscallArg(int i) = 0;
249 // used to shift args for indirect syscall
250 virtual void setSyscallArg(int i, IntReg val) = 0;
252 virtual void setSyscallReturn(SyscallReturn return_value) = 0;
254 // Same with st cond failures.
255 virtual Counter readFuncExeInst() = 0;
257 // This function exits the thread context in the CPU and returns
258 // 1 if the CPU has no more active threads (meaning it's OK to exit);
259 // Used in syscall-emulation mode when a thread calls the exit syscall.
260 virtual int exit() { return 1; };
263 virtual void changeRegFileContext(TheISA::RegContextParam param,
264 TheISA::RegContextVal val) = 0;
268 * ProxyThreadContext class that provides a way to implement a
269 * ThreadContext without having to derive from it. ThreadContext is an
270 * abstract class, so anything that derives from it and uses its
271 * interface will pay the overhead of virtual function calls. This
272 * class is created to enable a user-defined Thread object to be used
273 * wherever ThreadContexts are used, without paying the overhead of
274 * virtual function calls when it is used by itself. See
275 * simple_thread.hh for an example of this.
278 class ProxyThreadContext : public ThreadContext
281 ProxyThreadContext(TC *actual_tc)
282 { actualTC = actual_tc; }
289 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
291 void setCpuId(int id) { actualTC->setCpuId(id); }
293 int readCpuId() { return actualTC->readCpuId(); }
296 System *getSystemPtr() { return actualTC->getSystemPtr(); }
298 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
300 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
302 TheISA::Kernel::Statistics *getKernelStats()
303 { return actualTC->getKernelStats(); }
305 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
307 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
309 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
311 void connectMemPorts() { actualTC->connectMemPorts(); }
313 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
315 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
318 Status status() const { return actualTC->status(); }
320 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
322 /// Set the status to Active. Optional delay indicates number of
323 /// cycles to wait before beginning execution.
324 void activate(int delay = 1) { actualTC->activate(delay); }
326 /// Set the status to Suspended.
327 void suspend() { actualTC->suspend(); }
329 /// Set the status to Unallocated.
330 void deallocate(int delay = 0) { actualTC->deallocate(); }
332 /// Set the status to Halted.
333 void halt() { actualTC->halt(); }
336 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
339 void takeOverFrom(ThreadContext *oldContext)
340 { actualTC->takeOverFrom(oldContext); }
342 void regStats(const std::string &name) { actualTC->regStats(name); }
344 void serialize(std::ostream &os) { actualTC->serialize(os); }
345 void unserialize(Checkpoint *cp, const std::string §ion)
346 { actualTC->unserialize(cp, section); }
349 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
351 Tick readLastActivate() { return actualTC->readLastActivate(); }
352 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
354 void profileClear() { return actualTC->profileClear(); }
355 void profileSample() { return actualTC->profileSample(); }
358 int getThreadNum() { return actualTC->getThreadNum(); }
360 // @todo: Do I need this?
361 MachInst getInst() { return actualTC->getInst(); }
363 // @todo: Do I need this?
364 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
366 void clearArchRegs() { actualTC->clearArchRegs(); }
369 // New accessors for new decoder.
371 uint64_t readIntReg(int reg_idx)
372 { return actualTC->readIntReg(reg_idx); }
374 FloatReg readFloatReg(int reg_idx, int width)
375 { return actualTC->readFloatReg(reg_idx, width); }
377 FloatReg readFloatReg(int reg_idx)
378 { return actualTC->readFloatReg(reg_idx); }
380 FloatRegBits readFloatRegBits(int reg_idx, int width)
381 { return actualTC->readFloatRegBits(reg_idx, width); }
383 FloatRegBits readFloatRegBits(int reg_idx)
384 { return actualTC->readFloatRegBits(reg_idx); }
386 void setIntReg(int reg_idx, uint64_t val)
387 { actualTC->setIntReg(reg_idx, val); }
389 void setFloatReg(int reg_idx, FloatReg val, int width)
390 { actualTC->setFloatReg(reg_idx, val, width); }
392 void setFloatReg(int reg_idx, FloatReg val)
393 { actualTC->setFloatReg(reg_idx, val); }
395 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
396 { actualTC->setFloatRegBits(reg_idx, val, width); }
398 void setFloatRegBits(int reg_idx, FloatRegBits val)
399 { actualTC->setFloatRegBits(reg_idx, val); }
401 uint64_t readPC() { return actualTC->readPC(); }
403 void setPC(uint64_t val) { actualTC->setPC(val); }
405 uint64_t readNextPC() { return actualTC->readNextPC(); }
407 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
409 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
411 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
413 MiscReg readMiscReg(int misc_reg)
414 { return actualTC->readMiscReg(misc_reg); }
416 MiscReg readMiscRegWithEffect(int misc_reg)
417 { return actualTC->readMiscRegWithEffect(misc_reg); }
419 void setMiscReg(int misc_reg, const MiscReg &val)
420 { return actualTC->setMiscReg(misc_reg, val); }
422 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
423 { return actualTC->setMiscRegWithEffect(misc_reg, val); }
425 unsigned readStCondFailures()
426 { return actualTC->readStCondFailures(); }
428 void setStCondFailures(unsigned sc_failures)
429 { actualTC->setStCondFailures(sc_failures); }
432 bool misspeculating() { return actualTC->misspeculating(); }
435 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
437 // used to shift args for indirect syscall
438 void setSyscallArg(int i, IntReg val)
439 { actualTC->setSyscallArg(i, val); }
441 void setSyscallReturn(SyscallReturn return_value)
442 { actualTC->setSyscallReturn(return_value); }
444 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
447 void changeRegFileContext(TheISA::RegContextParam param,
448 TheISA::RegContextVal val)
450 actualTC->changeRegFileContext(param, val);