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42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
48 #include "arch/generic/isa.hh"
49 #include "arch/registers.hh"
50 #include "arch/types.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
53 #include "cpu/pc_event.hh"
54 #include "cpu/reg_class.hh"
56 // @todo: Figure out a more architecture independent way to obtain the ITB and
67 class EndQuiesceEvent;
76 * ThreadContext is the external interface to all thread state for
77 * anything outside of the CPU. It provides all accessor methods to
78 * state that might be needed by external objects, ranging from
79 * register values to things such as kernel stats. It is an abstract
80 * base class; the CPU can create its own ThreadContext by
83 * The ThreadContext is slightly different than the ExecContext. The
84 * ThreadContext provides access to an individual thread's state; an
85 * ExecContext provides ISA access to the CPU (meaning it is
86 * implicitly multithreaded on SMT systems). Additionally the
87 * ThreadState is an abstract class that exactly defines the
88 * interface; the ExecContext is a more implicit interface that must
89 * be implemented so that the ISA can access whatever state it needs.
91 class ThreadContext : public PCEventScope
94 typedef TheISA::MachInst MachInst;
95 using VecRegContainer = TheISA::VecRegContainer;
96 using VecElem = TheISA::VecElem;
97 using VecPredRegContainer = TheISA::VecPredRegContainer;
103 /// Running. Instructions should be executed only when
104 /// the context is in this state.
107 /// Temporarily inactive. Entered while waiting for
108 /// synchronization, etc.
111 /// Trying to exit and waiting for an event to completely exit.
112 /// Entered when target executes an exit syscall.
115 /// Permanently shut down. Entered when target executes
116 /// m5exit pseudo-instruction. When all contexts enter
117 /// this state, the simulation will terminate.
121 virtual ~ThreadContext() { };
123 virtual BaseCPU *getCpuPtr() = 0;
125 virtual int cpuId() const = 0;
127 virtual uint32_t socketId() const = 0;
129 virtual int threadId() const = 0;
131 virtual void setThreadId(int id) = 0;
133 virtual ContextID contextId() const = 0;
135 virtual void setContextId(ContextID id) = 0;
137 virtual BaseTLB *getITBPtr() = 0;
139 virtual BaseTLB *getDTBPtr() = 0;
141 virtual CheckerCPU *getCheckerCpuPtr() = 0;
143 virtual BaseISA *getIsaPtr() = 0;
145 virtual TheISA::Decoder *getDecoderPtr() = 0;
147 virtual System *getSystemPtr() = 0;
149 virtual ::Kernel::Statistics *getKernelStats() = 0;
151 virtual PortProxy &getPhysProxy() = 0;
153 virtual PortProxy &getVirtProxy() = 0;
156 * Initialise the physical and virtual port proxies and tie them to
157 * the data port of the CPU.
159 * tc ThreadContext for the virtual-to-physical translation
161 virtual void initMemProxies(ThreadContext *tc) = 0;
163 virtual Process *getProcessPtr() = 0;
165 virtual void setProcessPtr(Process *p) = 0;
167 virtual Status status() const = 0;
169 virtual void setStatus(Status new_status) = 0;
171 /// Set the status to Active.
172 virtual void activate() = 0;
174 /// Set the status to Suspended.
175 virtual void suspend() = 0;
177 /// Set the status to Halted.
178 virtual void halt() = 0;
180 /// Quiesce thread context
183 /// Quiesce, suspend, and schedule activate at resume
184 void quiesceTick(Tick resume);
186 virtual void dumpFuncProfile() = 0;
188 virtual void takeOverFrom(ThreadContext *old_context) = 0;
190 virtual void regStats(const std::string &name) = 0;
192 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
194 virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
195 virtual void descheduleInstCountEvent(Event *event) = 0;
196 virtual Tick getCurrentInstCount() = 0;
198 // Not necessarily the best location for these...
199 // Having an extra function just to read these is obnoxious
200 virtual Tick readLastActivate() = 0;
201 virtual Tick readLastSuspend() = 0;
203 virtual void profileClear() = 0;
204 virtual void profileSample() = 0;
206 virtual void copyArchRegs(ThreadContext *tc) = 0;
208 virtual void clearArchRegs() = 0;
211 // New accessors for new decoder.
213 virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
215 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
217 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
220 /** Vector Register Lane Interfaces. */
222 /** Reads source vector 8bit operand. */
223 virtual ConstVecLane8
224 readVec8BitLaneReg(const RegId& reg) const = 0;
226 /** Reads source vector 16bit operand. */
227 virtual ConstVecLane16
228 readVec16BitLaneReg(const RegId& reg) const = 0;
230 /** Reads source vector 32bit operand. */
231 virtual ConstVecLane32
232 readVec32BitLaneReg(const RegId& reg) const = 0;
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& reg) const = 0;
238 /** Write a lane of the destination vector register. */
239 virtual void setVecLane(const RegId& reg,
240 const LaneData<LaneSize::Byte>& val) = 0;
241 virtual void setVecLane(const RegId& reg,
242 const LaneData<LaneSize::TwoByte>& val) = 0;
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::FourByte>& val) = 0;
245 virtual void setVecLane(const RegId& reg,
246 const LaneData<LaneSize::EightByte>& val) = 0;
249 virtual const VecElem& readVecElem(const RegId& reg) const = 0;
251 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
253 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
255 virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
257 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
259 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
261 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
263 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
265 virtual void setVecPredReg(const RegId& reg,
266 const VecPredRegContainer& val) = 0;
268 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
270 virtual TheISA::PCState pcState() const = 0;
272 virtual void pcState(const TheISA::PCState &val) = 0;
277 TheISA::PCState pc_state = pcState();
278 pc_state.setNPC(val);
282 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
284 virtual Addr instAddr() const = 0;
286 virtual Addr nextInstAddr() const = 0;
288 virtual MicroPC microPC() const = 0;
290 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
292 virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
294 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
296 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
298 virtual RegId flattenRegId(const RegId& regId) const = 0;
300 // Also not necessarily the best location for these two. Hopefully will go
301 // away once we decide upon where st cond failures goes.
302 virtual unsigned readStCondFailures() const = 0;
304 virtual void setStCondFailures(unsigned sc_failures) = 0;
306 // Same with st cond failures.
307 virtual Counter readFuncExeInst() const = 0;
309 virtual void syscall(Fault *fault) = 0;
311 // This function exits the thread context in the CPU and returns
312 // 1 if the CPU has no more active threads (meaning it's OK to exit);
313 // Used in syscall-emulation mode when a thread calls the exit syscall.
314 virtual int exit() { return 1; };
316 /** function to compare two thread contexts (for debugging) */
317 static void compare(ThreadContext *one, ThreadContext *two);
321 * Flat register interfaces
323 * Some architectures have different registers visible in
324 * different modes. Such architectures "flatten" a register (see
325 * flattenRegId()) to map it into the
326 * gem5 register file. This interface provides a flat interface to
327 * the underlying register file, which allows for example
328 * serialization code to access all registers.
331 virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
332 virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
334 virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
335 virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
337 virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
338 virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
339 virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
341 virtual const VecElem& readVecElemFlat(RegIndex idx,
342 const ElemIndex& elemIdx) const = 0;
343 virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
344 const VecElem& val) = 0;
346 virtual const VecPredRegContainer &
347 readVecPredRegFlat(RegIndex idx) const = 0;
348 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
349 virtual void setVecPredRegFlat(RegIndex idx,
350 const VecPredRegContainer& val) = 0;
352 virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
353 virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
360 * Thread context serialization helpers
362 * These helper functions provide a way to the data in a
363 * ThreadContext. They are provided as separate helper function since
364 * implementing them as members of the ThreadContext interface would
365 * be confusing when the ThreadContext is exported via a proxy.
368 void serialize(const ThreadContext &tc, CheckpointOut &cp);
369 void unserialize(ThreadContext &tc, CheckpointIn &cp);
375 * Copy state between thread contexts in preparation for CPU handover.
377 * @note This method modifies the old thread contexts as well as the
378 * new thread context. The old thread context will have its quiesce
379 * event descheduled if it is scheduled and its status set to halted.
381 * @param new_tc Destination ThreadContext.
382 * @param old_tc Source ThreadContext.
384 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);