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44 #ifndef __CPU_THREAD_CONTEXT_HH__
45 #define __CPU_THREAD_CONTEXT_HH__
50 #include "arch/registers.hh"
51 #include "arch/types.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
55 // @todo: Figure out a more architecture independent way to obtain the ITB and
65 class EndQuiesceEvent;
66 class SETranslatingPortProxy;
67 class FSTranslatingPortProxy;
78 * ThreadContext is the external interface to all thread state for
79 * anything outside of the CPU. It provides all accessor methods to
80 * state that might be needed by external objects, ranging from
81 * register values to things such as kernel stats. It is an abstract
82 * base class; the CPU can create its own ThreadContext by either
83 * deriving from it, or using the templated ProxyThreadContext.
85 * The ThreadContext is slightly different than the ExecContext. The
86 * ThreadContext provides access to an individual thread's state; an
87 * ExecContext provides ISA access to the CPU (meaning it is
88 * implicitly multithreaded on SMT systems). Additionally the
89 * ThreadState is an abstract class that exactly defines the
90 * interface; the ExecContext is a more implicit interface that must
91 * be implemented so that the ISA can access whatever state it needs.
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::IntReg IntReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
100 typedef TheISA::CCReg CCReg;
101 typedef TheISA::MiscReg MiscReg;
106 /// Running. Instructions should be executed only when
107 /// the context is in this state.
110 /// Temporarily inactive. Entered while waiting for
111 /// synchronization, etc.
114 /// Permanently shut down. Entered when target executes
115 /// m5exit pseudo-instruction. When all contexts enter
116 /// this state, the simulation will terminate.
120 virtual ~ThreadContext() { };
122 virtual BaseCPU *getCpuPtr() = 0;
124 virtual int cpuId() = 0;
126 virtual int threadId() = 0;
128 virtual void setThreadId(int id) = 0;
130 virtual int contextId() = 0;
132 virtual void setContextId(int id) = 0;
134 virtual TheISA::TLB *getITBPtr() = 0;
136 virtual TheISA::TLB *getDTBPtr() = 0;
138 virtual CheckerCPU *getCheckerCpuPtr() = 0;
140 virtual TheISA::Decoder *getDecoderPtr() = 0;
142 virtual System *getSystemPtr() = 0;
144 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
146 virtual PortProxy &getPhysProxy() = 0;
148 virtual FSTranslatingPortProxy &getVirtProxy() = 0;
151 * Initialise the physical and virtual port proxies and tie them to
152 * the data port of the CPU.
154 * tc ThreadContext for the virtual-to-physical translation
156 virtual void initMemProxies(ThreadContext *tc) = 0;
158 virtual SETranslatingPortProxy &getMemProxy() = 0;
160 virtual Process *getProcessPtr() = 0;
162 virtual Status status() const = 0;
164 virtual void setStatus(Status new_status) = 0;
166 /// Set the status to Active. Optional delay indicates number of
167 /// cycles to wait before beginning execution.
168 virtual void activate(Cycles delay = Cycles(1)) = 0;
170 /// Set the status to Suspended.
171 virtual void suspend(Cycles delay = Cycles(0)) = 0;
173 /// Set the status to Halted.
174 virtual void halt(Cycles delay = Cycles(0)) = 0;
176 virtual void dumpFuncProfile() = 0;
178 virtual void takeOverFrom(ThreadContext *old_context) = 0;
180 virtual void regStats(const std::string &name) = 0;
182 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
184 // Not necessarily the best location for these...
185 // Having an extra function just to read these is obnoxious
186 virtual Tick readLastActivate() = 0;
187 virtual Tick readLastSuspend() = 0;
189 virtual void profileClear() = 0;
190 virtual void profileSample() = 0;
192 virtual void copyArchRegs(ThreadContext *tc) = 0;
194 virtual void clearArchRegs() = 0;
197 // New accessors for new decoder.
199 virtual uint64_t readIntReg(int reg_idx) = 0;
201 virtual FloatReg readFloatReg(int reg_idx) = 0;
203 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
205 virtual CCReg readCCReg(int reg_idx) = 0;
207 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
209 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
211 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
213 virtual void setCCReg(int reg_idx, CCReg val) = 0;
215 virtual TheISA::PCState pcState() = 0;
217 virtual void pcState(const TheISA::PCState &val) = 0;
219 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
221 virtual Addr instAddr() = 0;
223 virtual Addr nextInstAddr() = 0;
225 virtual MicroPC microPC() = 0;
227 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
229 virtual MiscReg readMiscReg(int misc_reg) = 0;
231 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
233 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
235 virtual int flattenIntIndex(int reg) = 0;
236 virtual int flattenFloatIndex(int reg) = 0;
237 virtual int flattenCCIndex(int reg) = 0;
238 virtual int flattenMiscIndex(int reg) = 0;
241 readRegOtherThread(int misc_reg, ThreadID tid)
247 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
251 // Also not necessarily the best location for these two. Hopefully will go
252 // away once we decide upon where st cond failures goes.
253 virtual unsigned readStCondFailures() = 0;
255 virtual void setStCondFailures(unsigned sc_failures) = 0;
257 // Only really makes sense for old CPU model. Still could be useful though.
258 virtual bool misspeculating() = 0;
260 // Same with st cond failures.
261 virtual Counter readFuncExeInst() = 0;
263 virtual void syscall(int64_t callnum) = 0;
265 // This function exits the thread context in the CPU and returns
266 // 1 if the CPU has no more active threads (meaning it's OK to exit);
267 // Used in syscall-emulation mode when a thread calls the exit syscall.
268 virtual int exit() { return 1; };
270 /** function to compare two thread contexts (for debugging) */
271 static void compare(ThreadContext *one, ThreadContext *two);
275 * Flat register interfaces
277 * Some architectures have different registers visible in
278 * different modes. Such architectures "flatten" a register (see
279 * flattenIntIndex() and flattenFloatIndex()) to map it into the
280 * gem5 register file. This interface provides a flat interface to
281 * the underlying register file, which allows for example
282 * serialization code to access all registers.
285 virtual uint64_t readIntRegFlat(int idx) = 0;
286 virtual void setIntRegFlat(int idx, uint64_t val) = 0;
288 virtual FloatReg readFloatRegFlat(int idx) = 0;
289 virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
291 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
292 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
294 virtual CCReg readCCRegFlat(int idx) = 0;
295 virtual void setCCRegFlat(int idx, CCReg val) = 0;
301 * ProxyThreadContext class that provides a way to implement a
302 * ThreadContext without having to derive from it. ThreadContext is an
303 * abstract class, so anything that derives from it and uses its
304 * interface will pay the overhead of virtual function calls. This
305 * class is created to enable a user-defined Thread object to be used
306 * wherever ThreadContexts are used, without paying the overhead of
307 * virtual function calls when it is used by itself. See
308 * simple_thread.hh for an example of this.
311 class ProxyThreadContext : public ThreadContext
314 ProxyThreadContext(TC *actual_tc)
315 { actualTC = actual_tc; }
322 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
324 int cpuId() { return actualTC->cpuId(); }
326 int threadId() { return actualTC->threadId(); }
328 void setThreadId(int id) { return actualTC->setThreadId(id); }
330 int contextId() { return actualTC->contextId(); }
332 void setContextId(int id) { actualTC->setContextId(id); }
334 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
336 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
338 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
340 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
342 System *getSystemPtr() { return actualTC->getSystemPtr(); }
344 TheISA::Kernel::Statistics *getKernelStats()
345 { return actualTC->getKernelStats(); }
347 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
349 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
351 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
353 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
355 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
357 Status status() const { return actualTC->status(); }
359 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
361 /// Set the status to Active. Optional delay indicates number of
362 /// cycles to wait before beginning execution.
363 void activate(Cycles delay = Cycles(1))
364 { actualTC->activate(delay); }
366 /// Set the status to Suspended.
367 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
369 /// Set the status to Halted.
370 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
372 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
374 void takeOverFrom(ThreadContext *oldContext)
375 { actualTC->takeOverFrom(oldContext); }
377 void regStats(const std::string &name) { actualTC->regStats(name); }
379 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
381 Tick readLastActivate() { return actualTC->readLastActivate(); }
382 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
384 void profileClear() { return actualTC->profileClear(); }
385 void profileSample() { return actualTC->profileSample(); }
387 // @todo: Do I need this?
388 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
390 void clearArchRegs() { actualTC->clearArchRegs(); }
393 // New accessors for new decoder.
395 uint64_t readIntReg(int reg_idx)
396 { return actualTC->readIntReg(reg_idx); }
398 FloatReg readFloatReg(int reg_idx)
399 { return actualTC->readFloatReg(reg_idx); }
401 FloatRegBits readFloatRegBits(int reg_idx)
402 { return actualTC->readFloatRegBits(reg_idx); }
404 CCReg readCCReg(int reg_idx)
405 { return actualTC->readCCReg(reg_idx); }
407 void setIntReg(int reg_idx, uint64_t val)
408 { actualTC->setIntReg(reg_idx, val); }
410 void setFloatReg(int reg_idx, FloatReg val)
411 { actualTC->setFloatReg(reg_idx, val); }
413 void setFloatRegBits(int reg_idx, FloatRegBits val)
414 { actualTC->setFloatRegBits(reg_idx, val); }
416 void setCCReg(int reg_idx, CCReg val)
417 { actualTC->setCCReg(reg_idx, val); }
419 TheISA::PCState pcState() { return actualTC->pcState(); }
421 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
423 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
425 Addr instAddr() { return actualTC->instAddr(); }
426 Addr nextInstAddr() { return actualTC->nextInstAddr(); }
427 MicroPC microPC() { return actualTC->microPC(); }
429 bool readPredicate() { return actualTC->readPredicate(); }
431 void setPredicate(bool val)
432 { actualTC->setPredicate(val); }
434 MiscReg readMiscRegNoEffect(int misc_reg)
435 { return actualTC->readMiscRegNoEffect(misc_reg); }
437 MiscReg readMiscReg(int misc_reg)
438 { return actualTC->readMiscReg(misc_reg); }
440 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
441 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
443 void setMiscReg(int misc_reg, const MiscReg &val)
444 { return actualTC->setMiscReg(misc_reg, val); }
446 int flattenIntIndex(int reg)
447 { return actualTC->flattenIntIndex(reg); }
449 int flattenFloatIndex(int reg)
450 { return actualTC->flattenFloatIndex(reg); }
452 int flattenCCIndex(int reg)
453 { return actualTC->flattenCCIndex(reg); }
455 int flattenMiscIndex(int reg)
456 { return actualTC->flattenMiscIndex(reg); }
458 unsigned readStCondFailures()
459 { return actualTC->readStCondFailures(); }
461 void setStCondFailures(unsigned sc_failures)
462 { actualTC->setStCondFailures(sc_failures); }
465 bool misspeculating() { return actualTC->misspeculating(); }
467 void syscall(int64_t callnum)
468 { actualTC->syscall(callnum); }
470 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
472 uint64_t readIntRegFlat(int idx)
473 { return actualTC->readIntRegFlat(idx); }
475 void setIntRegFlat(int idx, uint64_t val)
476 { actualTC->setIntRegFlat(idx, val); }
478 FloatReg readFloatRegFlat(int idx)
479 { return actualTC->readFloatRegFlat(idx); }
481 void setFloatRegFlat(int idx, FloatReg val)
482 { actualTC->setFloatRegFlat(idx, val); }
484 FloatRegBits readFloatRegBitsFlat(int idx)
485 { return actualTC->readFloatRegBitsFlat(idx); }
487 void setFloatRegBitsFlat(int idx, FloatRegBits val)
488 { actualTC->setFloatRegBitsFlat(idx, val); }
490 CCReg readCCRegFlat(int idx)
491 { return actualTC->readCCRegFlat(idx); }
493 void setCCRegFlat(int idx, CCReg val)
494 { actualTC->setCCRegFlat(idx, val); }
499 * Thread context serialization helpers
501 * These helper functions provide a way to the data in a
502 * ThreadContext. They are provided as separate helper function since
503 * implementing them as members of the ThreadContext interface would
504 * be confusing when the ThreadContext is exported via a proxy.
507 void serialize(ThreadContext &tc, std::ostream &os);
508 void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion);
514 * Copy state between thread contexts in preparation for CPU handover.
516 * @note This method modifies the old thread contexts as well as the
517 * new thread context. The old thread context will have its quiesce
518 * event descheduled if it is scheduled and its status set to halted.
520 * @param new_tc Destination ThreadContext.
521 * @param old_tc Source ThreadContext.
523 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);