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31 #ifndef __CPU_THREAD_CONTEXT_HH__
32 #define __CPU_THREAD_CONTEXT_HH__
34 #include "arch/regfile.hh"
35 #include "arch/types.hh"
36 #include "config/full_system.hh"
37 #include "mem/request.hh"
38 #include "sim/faults.hh"
39 #include "sim/host.hh"
40 #include "sim/serialize.hh"
41 #include "sim/byteswap.hh"
43 // @todo: Figure out a more architecture independent way to obtain the ITB and
50 class EndQuiesceEvent;
52 class TranslatingPort;
64 * ThreadContext is the external interface to all thread state for
65 * anything outside of the CPU. It provides all accessor methods to
66 * state that might be needed by external objects, ranging from
67 * register values to things such as kernel stats. It is an abstract
68 * base class; the CPU can create its own ThreadContext by either
69 * deriving from it, or using the templated ProxyThreadContext.
71 * The ThreadContext is slightly different than the ExecContext. The
72 * ThreadContext provides access to an individual thread's state; an
73 * ExecContext provides ISA access to the CPU (meaning it is
74 * implicitly multithreaded on SMT systems). Additionally the
75 * ThreadState is an abstract class that exactly defines the
76 * interface; the ExecContext is a more implicit interface that must
77 * be implemented so that the ISA can access whatever state it needs.
82 typedef TheISA::RegFile RegFile;
83 typedef TheISA::MachInst MachInst;
84 typedef TheISA::IntReg IntReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87 typedef TheISA::MiscRegFile MiscRegFile;
88 typedef TheISA::MiscReg MiscReg;
93 /// Running. Instructions should be executed only when
94 /// the context is in this state.
97 /// Temporarily inactive. Entered while waiting for
98 /// synchronization, etc.
101 /// Permanently shut down. Entered when target executes
102 /// m5exit pseudo-instruction. When all contexts enter
103 /// this state, the simulation will terminate.
107 virtual ~ThreadContext() { };
109 virtual BaseCPU *getCpuPtr() = 0;
111 virtual int cpuId() = 0;
113 virtual int threadId() = 0;
115 virtual void setThreadId(int id) = 0;
117 virtual int contextId() = 0;
119 virtual void setContextId(int id) = 0;
121 virtual TheISA::TLB *getITBPtr() = 0;
123 virtual TheISA::TLB *getDTBPtr() = 0;
125 virtual System *getSystemPtr() = 0;
128 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
130 virtual FunctionalPort *getPhysPort() = 0;
132 virtual VirtualPort *getVirtPort() = 0;
134 virtual void connectMemPorts(ThreadContext *tc) = 0;
136 virtual TranslatingPort *getMemPort() = 0;
138 virtual Process *getProcessPtr() = 0;
141 virtual Status status() const = 0;
143 virtual void setStatus(Status new_status) = 0;
145 /// Set the status to Active. Optional delay indicates number of
146 /// cycles to wait before beginning execution.
147 virtual void activate(int delay = 1) = 0;
149 /// Set the status to Suspended.
150 virtual void suspend(int delay = 0) = 0;
152 /// Set the status to Halted.
153 virtual void halt(int delay = 0) = 0;
156 virtual void dumpFuncProfile() = 0;
159 virtual void takeOverFrom(ThreadContext *old_context) = 0;
161 virtual void regStats(const std::string &name) = 0;
163 virtual void serialize(std::ostream &os) = 0;
164 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
167 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
169 // Not necessarily the best location for these...
170 // Having an extra function just to read these is obnoxious
171 virtual Tick readLastActivate() = 0;
172 virtual Tick readLastSuspend() = 0;
174 virtual void profileClear() = 0;
175 virtual void profileSample() = 0;
178 // Also somewhat obnoxious. Really only used for the TLB fault.
179 // However, may be quite useful in SPARC.
180 virtual TheISA::MachInst getInst() = 0;
182 virtual void copyArchRegs(ThreadContext *tc) = 0;
184 virtual void clearArchRegs() = 0;
187 // New accessors for new decoder.
189 virtual uint64_t readIntReg(int reg_idx) = 0;
191 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
193 virtual FloatReg readFloatReg(int reg_idx) = 0;
195 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
197 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
199 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
201 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
203 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
209 virtual uint64_t readPC() = 0;
211 virtual void setPC(uint64_t val) = 0;
213 virtual uint64_t readNextPC() = 0;
215 virtual void setNextPC(uint64_t val) = 0;
217 virtual uint64_t readNextNPC() = 0;
219 virtual void setNextNPC(uint64_t val) = 0;
221 virtual uint64_t readMicroPC() = 0;
223 virtual void setMicroPC(uint64_t val) = 0;
225 virtual uint64_t readNextMicroPC() = 0;
227 virtual void setNextMicroPC(uint64_t val) = 0;
229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
231 virtual MiscReg readMiscReg(int misc_reg) = 0;
233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
241 // Also not necessarily the best location for these two. Hopefully will go
242 // away once we decide upon where st cond failures goes.
243 virtual unsigned readStCondFailures() = 0;
245 virtual void setStCondFailures(unsigned sc_failures) = 0;
247 // Only really makes sense for old CPU model. Still could be useful though.
248 virtual bool misspeculating() = 0;
251 // Same with st cond failures.
252 virtual Counter readFuncExeInst() = 0;
254 virtual void syscall(int64_t callnum) = 0;
256 // This function exits the thread context in the CPU and returns
257 // 1 if the CPU has no more active threads (meaning it's OK to exit);
258 // Used in syscall-emulation mode when a thread calls the exit syscall.
259 virtual int exit() { return 1; };
262 /** function to compare two thread contexts (for debugging) */
263 static void compare(ThreadContext *one, ThreadContext *two);
267 * ProxyThreadContext class that provides a way to implement a
268 * ThreadContext without having to derive from it. ThreadContext is an
269 * abstract class, so anything that derives from it and uses its
270 * interface will pay the overhead of virtual function calls. This
271 * class is created to enable a user-defined Thread object to be used
272 * wherever ThreadContexts are used, without paying the overhead of
273 * virtual function calls when it is used by itself. See
274 * simple_thread.hh for an example of this.
277 class ProxyThreadContext : public ThreadContext
280 ProxyThreadContext(TC *actual_tc)
281 { actualTC = actual_tc; }
288 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
290 int cpuId() { return actualTC->cpuId(); }
292 int threadId() { return actualTC->threadId(); }
294 void setThreadId(int id) { return actualTC->setThreadId(id); }
296 int contextId() { return actualTC->contextId(); }
298 void setContextId(int id) { actualTC->setContextId(id); }
300 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
302 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
304 System *getSystemPtr() { return actualTC->getSystemPtr(); }
307 TheISA::Kernel::Statistics *getKernelStats()
308 { return actualTC->getKernelStats(); }
310 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
312 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
314 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
316 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
318 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
321 Status status() const { return actualTC->status(); }
323 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
325 /// Set the status to Active. Optional delay indicates number of
326 /// cycles to wait before beginning execution.
327 void activate(int delay = 1) { actualTC->activate(delay); }
329 /// Set the status to Suspended.
330 void suspend(int delay = 0) { actualTC->suspend(); }
332 /// Set the status to Halted.
333 void halt(int delay = 0) { actualTC->halt(); }
336 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
339 void takeOverFrom(ThreadContext *oldContext)
340 { actualTC->takeOverFrom(oldContext); }
342 void regStats(const std::string &name) { actualTC->regStats(name); }
344 void serialize(std::ostream &os) { actualTC->serialize(os); }
345 void unserialize(Checkpoint *cp, const std::string §ion)
346 { actualTC->unserialize(cp, section); }
349 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
351 Tick readLastActivate() { return actualTC->readLastActivate(); }
352 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
354 void profileClear() { return actualTC->profileClear(); }
355 void profileSample() { return actualTC->profileSample(); }
357 // @todo: Do I need this?
358 MachInst getInst() { return actualTC->getInst(); }
360 // @todo: Do I need this?
361 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
363 void clearArchRegs() { actualTC->clearArchRegs(); }
366 // New accessors for new decoder.
368 uint64_t readIntReg(int reg_idx)
369 { return actualTC->readIntReg(reg_idx); }
371 FloatReg readFloatReg(int reg_idx, int width)
372 { return actualTC->readFloatReg(reg_idx, width); }
374 FloatReg readFloatReg(int reg_idx)
375 { return actualTC->readFloatReg(reg_idx); }
377 FloatRegBits readFloatRegBits(int reg_idx, int width)
378 { return actualTC->readFloatRegBits(reg_idx, width); }
380 FloatRegBits readFloatRegBits(int reg_idx)
381 { return actualTC->readFloatRegBits(reg_idx); }
383 void setIntReg(int reg_idx, uint64_t val)
384 { actualTC->setIntReg(reg_idx, val); }
386 void setFloatReg(int reg_idx, FloatReg val, int width)
387 { actualTC->setFloatReg(reg_idx, val, width); }
389 void setFloatReg(int reg_idx, FloatReg val)
390 { actualTC->setFloatReg(reg_idx, val); }
392 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
393 { actualTC->setFloatRegBits(reg_idx, val, width); }
395 void setFloatRegBits(int reg_idx, FloatRegBits val)
396 { actualTC->setFloatRegBits(reg_idx, val); }
398 uint64_t readPC() { return actualTC->readPC(); }
400 void setPC(uint64_t val) { actualTC->setPC(val); }
402 uint64_t readNextPC() { return actualTC->readNextPC(); }
404 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
406 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
408 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
410 uint64_t readMicroPC() { return actualTC->readMicroPC(); }
412 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
414 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
416 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
418 MiscReg readMiscRegNoEffect(int misc_reg)
419 { return actualTC->readMiscRegNoEffect(misc_reg); }
421 MiscReg readMiscReg(int misc_reg)
422 { return actualTC->readMiscReg(misc_reg); }
424 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
425 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
427 void setMiscReg(int misc_reg, const MiscReg &val)
428 { return actualTC->setMiscReg(misc_reg, val); }
430 unsigned readStCondFailures()
431 { return actualTC->readStCondFailures(); }
433 void setStCondFailures(unsigned sc_failures)
434 { actualTC->setStCondFailures(sc_failures); }
437 bool misspeculating() { return actualTC->misspeculating(); }
440 void syscall(int64_t callnum)
441 { actualTC->syscall(callnum); }
443 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }