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31 #ifndef __CPU_THREAD_CONTEXT_HH__
32 #define __CPU_THREAD_CONTEXT_HH__
34 #include "arch/regfile.hh"
35 #include "arch/types.hh"
36 #include "config/full_system.hh"
37 #include "mem/request.hh"
38 #include "sim/faults.hh"
39 #include "sim/host.hh"
40 #include "sim/serialize.hh"
41 #include "sim/byteswap.hh"
43 // @todo: Figure out a more architecture independent way to obtain the ITB and
51 class EndQuiesceEvent;
53 class TranslatingPort;
65 * ThreadContext is the external interface to all thread state for
66 * anything outside of the CPU. It provides all accessor methods to
67 * state that might be needed by external objects, ranging from
68 * register values to things such as kernel stats. It is an abstract
69 * base class; the CPU can create its own ThreadContext by either
70 * deriving from it, or using the templated ProxyThreadContext.
72 * The ThreadContext is slightly different than the ExecContext. The
73 * ThreadContext provides access to an individual thread's state; an
74 * ExecContext provides ISA access to the CPU (meaning it is
75 * implicitly multithreaded on SMT systems). Additionally the
76 * ThreadState is an abstract class that exactly defines the
77 * interface; the ExecContext is a more implicit interface that must
78 * be implemented so that the ISA can access whatever state it needs.
83 typedef TheISA::RegFile RegFile;
84 typedef TheISA::MachInst MachInst;
85 typedef TheISA::IntReg IntReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::MiscRegFile MiscRegFile;
89 typedef TheISA::MiscReg MiscReg;
93 /// Initialized but not running yet. All CPUs start in
94 /// this state, but most transition to Active on cycle 1.
95 /// In MP or SMT systems, non-primary contexts will stay
96 /// in this state until a thread is assigned to them.
99 /// Running. Instructions should be executed only when
100 /// the context is in this state.
103 /// Temporarily inactive. Entered while waiting for
104 /// synchronization, etc.
107 /// Permanently shut down. Entered when target executes
108 /// m5exit pseudo-instruction. When all contexts enter
109 /// this state, the simulation will terminate.
113 virtual ~ThreadContext() { };
115 virtual BaseCPU *getCpuPtr() = 0;
117 virtual int cpuId() = 0;
119 virtual int threadId() = 0;
121 virtual void setThreadId(int id) = 0;
123 virtual int contextId() = 0;
125 virtual void setContextId(int id) = 0;
127 virtual TheISA::ITB *getITBPtr() = 0;
129 virtual TheISA::DTB *getDTBPtr() = 0;
131 virtual System *getSystemPtr() = 0;
134 virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
136 virtual FunctionalPort *getPhysPort() = 0;
138 virtual VirtualPort *getVirtPort() = 0;
140 virtual void connectMemPorts(ThreadContext *tc) = 0;
142 virtual TranslatingPort *getMemPort() = 0;
144 virtual Process *getProcessPtr() = 0;
147 virtual Status status() const = 0;
149 virtual void setStatus(Status new_status) = 0;
151 /// Set the status to Active. Optional delay indicates number of
152 /// cycles to wait before beginning execution.
153 virtual void activate(int delay = 1) = 0;
155 /// Set the status to Suspended.
156 virtual void suspend(int delay = 0) = 0;
158 /// Set the status to Unallocated.
159 virtual void deallocate(int delay = 0) = 0;
161 /// Set the status to Halted.
162 virtual void halt(int delay = 0) = 0;
165 virtual void dumpFuncProfile() = 0;
168 virtual void takeOverFrom(ThreadContext *old_context) = 0;
170 virtual void regStats(const std::string &name) = 0;
172 virtual void serialize(std::ostream &os) = 0;
173 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
176 virtual EndQuiesceEvent *getQuiesceEvent() = 0;
178 // Not necessarily the best location for these...
179 // Having an extra function just to read these is obnoxious
180 virtual Tick readLastActivate() = 0;
181 virtual Tick readLastSuspend() = 0;
183 virtual void profileClear() = 0;
184 virtual void profileSample() = 0;
187 // Also somewhat obnoxious. Really only used for the TLB fault.
188 // However, may be quite useful in SPARC.
189 virtual TheISA::MachInst getInst() = 0;
191 virtual void copyArchRegs(ThreadContext *tc) = 0;
193 virtual void clearArchRegs() = 0;
196 // New accessors for new decoder.
198 virtual uint64_t readIntReg(int reg_idx) = 0;
200 virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
202 virtual FloatReg readFloatReg(int reg_idx) = 0;
204 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
206 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
208 virtual void setIntReg(int reg_idx, uint64_t val) = 0;
210 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
212 virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
214 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
216 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
218 virtual uint64_t readPC() = 0;
220 virtual void setPC(uint64_t val) = 0;
222 virtual uint64_t readNextPC() = 0;
224 virtual void setNextPC(uint64_t val) = 0;
226 virtual uint64_t readNextNPC() = 0;
228 virtual void setNextNPC(uint64_t val) = 0;
230 virtual uint64_t readMicroPC() = 0;
232 virtual void setMicroPC(uint64_t val) = 0;
234 virtual uint64_t readNextMicroPC() = 0;
236 virtual void setNextMicroPC(uint64_t val) = 0;
238 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
240 virtual MiscReg readMiscReg(int misc_reg) = 0;
242 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
244 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
246 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
248 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
250 // Also not necessarily the best location for these two. Hopefully will go
251 // away once we decide upon where st cond failures goes.
252 virtual unsigned readStCondFailures() = 0;
254 virtual void setStCondFailures(unsigned sc_failures) = 0;
256 // Only really makes sense for old CPU model. Still could be useful though.
257 virtual bool misspeculating() = 0;
260 // Same with st cond failures.
261 virtual Counter readFuncExeInst() = 0;
263 virtual void syscall(int64_t callnum) = 0;
265 // This function exits the thread context in the CPU and returns
266 // 1 if the CPU has no more active threads (meaning it's OK to exit);
267 // Used in syscall-emulation mode when a thread calls the exit syscall.
268 virtual int exit() { return 1; };
271 /** function to compare two thread contexts (for debugging) */
272 static void compare(ThreadContext *one, ThreadContext *two);
276 * ProxyThreadContext class that provides a way to implement a
277 * ThreadContext without having to derive from it. ThreadContext is an
278 * abstract class, so anything that derives from it and uses its
279 * interface will pay the overhead of virtual function calls. This
280 * class is created to enable a user-defined Thread object to be used
281 * wherever ThreadContexts are used, without paying the overhead of
282 * virtual function calls when it is used by itself. See
283 * simple_thread.hh for an example of this.
286 class ProxyThreadContext : public ThreadContext
289 ProxyThreadContext(TC *actual_tc)
290 { actualTC = actual_tc; }
297 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
299 int cpuId() { return actualTC->cpuId(); }
301 int threadId() { return actualTC->threadId(); }
303 void setThreadId(int id) { return actualTC->setThreadId(id); }
305 int contextId() { return actualTC->contextId(); }
307 void setContextId(int id) { actualTC->setContextId(id); }
309 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
311 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
313 System *getSystemPtr() { return actualTC->getSystemPtr(); }
316 TheISA::Kernel::Statistics *getKernelStats()
317 { return actualTC->getKernelStats(); }
319 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
321 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
323 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
325 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
327 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
330 Status status() const { return actualTC->status(); }
332 void setStatus(Status new_status) { actualTC->setStatus(new_status); }
334 /// Set the status to Active. Optional delay indicates number of
335 /// cycles to wait before beginning execution.
336 void activate(int delay = 1) { actualTC->activate(delay); }
338 /// Set the status to Suspended.
339 void suspend(int delay = 0) { actualTC->suspend(); }
341 /// Set the status to Unallocated.
342 void deallocate(int delay = 0) { actualTC->deallocate(); }
344 /// Set the status to Halted.
345 void halt(int delay = 0) { actualTC->halt(); }
348 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
351 void takeOverFrom(ThreadContext *oldContext)
352 { actualTC->takeOverFrom(oldContext); }
354 void regStats(const std::string &name) { actualTC->regStats(name); }
356 void serialize(std::ostream &os) { actualTC->serialize(os); }
357 void unserialize(Checkpoint *cp, const std::string §ion)
358 { actualTC->unserialize(cp, section); }
361 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
363 Tick readLastActivate() { return actualTC->readLastActivate(); }
364 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
366 void profileClear() { return actualTC->profileClear(); }
367 void profileSample() { return actualTC->profileSample(); }
369 // @todo: Do I need this?
370 MachInst getInst() { return actualTC->getInst(); }
372 // @todo: Do I need this?
373 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
375 void clearArchRegs() { actualTC->clearArchRegs(); }
378 // New accessors for new decoder.
380 uint64_t readIntReg(int reg_idx)
381 { return actualTC->readIntReg(reg_idx); }
383 FloatReg readFloatReg(int reg_idx, int width)
384 { return actualTC->readFloatReg(reg_idx, width); }
386 FloatReg readFloatReg(int reg_idx)
387 { return actualTC->readFloatReg(reg_idx); }
389 FloatRegBits readFloatRegBits(int reg_idx, int width)
390 { return actualTC->readFloatRegBits(reg_idx, width); }
392 FloatRegBits readFloatRegBits(int reg_idx)
393 { return actualTC->readFloatRegBits(reg_idx); }
395 void setIntReg(int reg_idx, uint64_t val)
396 { actualTC->setIntReg(reg_idx, val); }
398 void setFloatReg(int reg_idx, FloatReg val, int width)
399 { actualTC->setFloatReg(reg_idx, val, width); }
401 void setFloatReg(int reg_idx, FloatReg val)
402 { actualTC->setFloatReg(reg_idx, val); }
404 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
405 { actualTC->setFloatRegBits(reg_idx, val, width); }
407 void setFloatRegBits(int reg_idx, FloatRegBits val)
408 { actualTC->setFloatRegBits(reg_idx, val); }
410 uint64_t readPC() { return actualTC->readPC(); }
412 void setPC(uint64_t val) { actualTC->setPC(val); }
414 uint64_t readNextPC() { return actualTC->readNextPC(); }
416 void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
418 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
420 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
422 uint64_t readMicroPC() { return actualTC->readMicroPC(); }
424 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
426 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
428 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); }
430 MiscReg readMiscRegNoEffect(int misc_reg)
431 { return actualTC->readMiscRegNoEffect(misc_reg); }
433 MiscReg readMiscReg(int misc_reg)
434 { return actualTC->readMiscReg(misc_reg); }
436 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
437 { return actualTC->setMiscRegNoEffect(misc_reg, val); }
439 void setMiscReg(int misc_reg, const MiscReg &val)
440 { return actualTC->setMiscReg(misc_reg, val); }
442 unsigned readStCondFailures()
443 { return actualTC->readStCondFailures(); }
445 void setStCondFailures(unsigned sc_failures)
446 { actualTC->setStCondFailures(sc_failures); }
449 bool misspeculating() { return actualTC->misspeculating(); }
452 void syscall(int64_t callnum)
453 { actualTC->syscall(callnum); }
455 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }