src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_THREAD_CONTEXT_HH__
  32 #define __CPU_THREAD_CONTEXT_HH__
  33
  34 #include <iostream>
  35 #include <string>
  36
  37 #include "arch/registers.hh"
  38 #include "arch/types.hh"
  39 #include "base/types.hh"
  40 #include "config/the_isa.hh"
  41
  42 // @todo: Figure out a more architecture independent way to obtain the ITB and
  43 // DTB pointers.
  44 namespace TheISA
  45 {
  46     class TLB;
  47 }
  48 class BaseCPU;
  49 class Checkpoint;
  50 class Decoder;
  51 class EndQuiesceEvent;
  52 class SETranslatingPortProxy;
  53 class FSTranslatingPortProxy;
  54 class PortProxy;
  55 class Process;
  56 class System;
  57 namespace TheISA {
  58     namespace Kernel {
  59         class Statistics;
  60     };
  61 };
  62
  63 /**
  64  * ThreadContext is the external interface to all thread state for
  65  * anything outside of the CPU. It provides all accessor methods to
  66  * state that might be needed by external objects, ranging from
  67  * register values to things such as kernel stats. It is an abstract
  68  * base class; the CPU can create its own ThreadContext by either
  69  * deriving from it, or using the templated ProxyThreadContext.
  70  *
  71  * The ThreadContext is slightly different than the ExecContext.  The
  72  * ThreadContext provides access to an individual thread's state; an
  73  * ExecContext provides ISA access to the CPU (meaning it is
  74  * implicitly multithreaded on SMT systems).  Additionally the
  75  * ThreadState is an abstract class that exactly defines the
  76  * interface; the ExecContext is a more implicit interface that must
  77  * be implemented so that the ISA can access whatever state it needs.
  78  */
  79 class ThreadContext
  80 {
  81   protected:
  82     typedef TheISA::MachInst MachInst;
  83     typedef TheISA::IntReg IntReg;
  84     typedef TheISA::FloatReg FloatReg;
  85     typedef TheISA::FloatRegBits FloatRegBits;
  86     typedef TheISA::MiscReg MiscReg;
  87   public:
  88
  89     enum Status
  90     {
  91         /// Running.  Instructions should be executed only when
  92         /// the context is in this state.
  93         Active,
  94
  95         /// Temporarily inactive.  Entered while waiting for
  96         /// synchronization, etc.
  97         Suspended,
  98
  99         /// Permanently shut down.  Entered when target executes
 100         /// m5exit pseudo-instruction.  When all contexts enter
 101         /// this state, the simulation will terminate.
 102         Halted
 103     };
 104
 105     virtual ~ThreadContext() { };
 106
 107     virtual BaseCPU *getCpuPtr() = 0;
 108
 109     virtual int cpuId() = 0;
 110
 111     virtual int threadId() = 0;
 112
 113     virtual void setThreadId(int id) = 0;
 114
 115     virtual int contextId() = 0;
 116
 117     virtual void setContextId(int id) = 0;
 118
 119     virtual TheISA::TLB *getITBPtr() = 0;
 120
 121     virtual TheISA::TLB *getDTBPtr() = 0;
 122
 123     virtual Decoder *getDecoderPtr() = 0;
 124
 125     virtual System *getSystemPtr() = 0;
 126
 127     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 128
 129     virtual PortProxy* getPhysProxy() = 0;
 130
 131     virtual FSTranslatingPortProxy* getVirtProxy() = 0;
 132
 133     /**
 134      * Initialise the physical and virtual port proxies and tie them to
 135      * the data port of the CPU.
 136      *
 137      * tc ThreadContext for the virtual-to-physical translation
 138      */
 139     virtual void initMemProxies(ThreadContext *tc) = 0;
 140
 141     virtual SETranslatingPortProxy *getMemProxy() = 0;
 142
 143     virtual Process *getProcessPtr() = 0;
 144
 145     virtual Status status() const = 0;
 146
 147     virtual void setStatus(Status new_status) = 0;
 148
 149     /// Set the status to Active.  Optional delay indicates number of
 150     /// cycles to wait before beginning execution.
 151     virtual void activate(int delay = 1) = 0;
 152
 153     /// Set the status to Suspended.
 154     virtual void suspend(int delay = 0) = 0;
 155
 156     /// Set the status to Halted.
 157     virtual void halt(int delay = 0) = 0;
 158
 159     virtual void dumpFuncProfile() = 0;
 160
 161     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 162
 163     virtual void regStats(const std::string &name) = 0;
 164
 165     virtual void serialize(std::ostream &os) = 0;
 166     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 167
 168     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 169
 170     // Not necessarily the best location for these...
 171     // Having an extra function just to read these is obnoxious
 172     virtual Tick readLastActivate() = 0;
 173     virtual Tick readLastSuspend() = 0;
 174
 175     virtual void profileClear() = 0;
 176     virtual void profileSample() = 0;
 177
 178     virtual void copyArchRegs(ThreadContext *tc) = 0;
 179
 180     virtual void clearArchRegs() = 0;
 181
 182     //
 183     // New accessors for new decoder.
 184     //
 185     virtual uint64_t readIntReg(int reg_idx) = 0;
 186
 187     virtual FloatReg readFloatReg(int reg_idx) = 0;
 188
 189     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 190
 191     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 192
 193     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 194
 195     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 196
 197     virtual TheISA::PCState pcState() = 0;
 198
 199     virtual void pcState(const TheISA::PCState &val) = 0;
 200
 201     virtual Addr instAddr() = 0;
 202
 203     virtual Addr nextInstAddr() = 0;
 204
 205     virtual MicroPC microPC() = 0;
 206
 207     virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
 208
 209     virtual MiscReg readMiscReg(int misc_reg) = 0;
 210
 211     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
 212
 213     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 214
 215     virtual int flattenIntIndex(int reg) = 0;
 216     virtual int flattenFloatIndex(int reg) = 0;
 217
 218     virtual uint64_t
 219     readRegOtherThread(int misc_reg, ThreadID tid)
 220     {
 221         return 0;
 222     }
 223
 224     virtual void
 225     setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
 226     {
 227     }
 228
 229     // Also not necessarily the best location for these two.  Hopefully will go
 230     // away once we decide upon where st cond failures goes.
 231     virtual unsigned readStCondFailures() = 0;
 232
 233     virtual void setStCondFailures(unsigned sc_failures) = 0;
 234
 235     // Only really makes sense for old CPU model.  Still could be useful though.
 236     virtual bool misspeculating() = 0;
 237
 238     // Same with st cond failures.
 239     virtual Counter readFuncExeInst() = 0;
 240
 241     virtual void syscall(int64_t callnum) = 0;
 242
 243     // This function exits the thread context in the CPU and returns
 244     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 245     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 246     virtual int exit() { return 1; };
 247
 248     /** function to compare two thread contexts (for debugging) */
 249     static void compare(ThreadContext *one, ThreadContext *two);
 250 };
 251
 252 /**
 253  * ProxyThreadContext class that provides a way to implement a
 254  * ThreadContext without having to derive from it. ThreadContext is an
 255  * abstract class, so anything that derives from it and uses its
 256  * interface will pay the overhead of virtual function calls.  This
 257  * class is created to enable a user-defined Thread object to be used
 258  * wherever ThreadContexts are used, without paying the overhead of
 259  * virtual function calls when it is used by itself.  See
 260  * simple_thread.hh for an example of this.
 261  */
 262 template <class TC>
 263 class ProxyThreadContext : public ThreadContext
 264 {
 265   public:
 266     ProxyThreadContext(TC *actual_tc)
 267     { actualTC = actual_tc; }
 268
 269   private:
 270     TC *actualTC;
 271
 272   public:
 273
 274     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 275
 276     int cpuId() { return actualTC->cpuId(); }
 277
 278     int threadId() { return actualTC->threadId(); }
 279
 280     void setThreadId(int id) { return actualTC->setThreadId(id); }
 281
 282     int contextId() { return actualTC->contextId(); }
 283
 284     void setContextId(int id) { actualTC->setContextId(id); }
 285
 286     TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
 287
 288     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 289
 290     Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 291
 292     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 293
 294     TheISA::Kernel::Statistics *getKernelStats()
 295     { return actualTC->getKernelStats(); }
 296
 297     PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
 298
 299     FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); }
 300
 301     void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
 302
 303     SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
 304
 305     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 306
 307     Status status() const { return actualTC->status(); }
 308
 309     void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 310
 311     /// Set the status to Active.  Optional delay indicates number of
 312     /// cycles to wait before beginning execution.
 313     void activate(int delay = 1) { actualTC->activate(delay); }
 314
 315     /// Set the status to Suspended.
 316     void suspend(int delay = 0) { actualTC->suspend(); }
 317
 318     /// Set the status to Halted.
 319     void halt(int delay = 0) { actualTC->halt(); }
 320
 321     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 322
 323     void takeOverFrom(ThreadContext *oldContext)
 324     { actualTC->takeOverFrom(oldContext); }
 325
 326     void regStats(const std::string &name) { actualTC->regStats(name); }
 327
 328     void serialize(std::ostream &os) { actualTC->serialize(os); }
 329     void unserialize(Checkpoint *cp, const std::string &section)
 330     { actualTC->unserialize(cp, section); }
 331
 332     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 333
 334     Tick readLastActivate() { return actualTC->readLastActivate(); }
 335     Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 336
 337     void profileClear() { return actualTC->profileClear(); }
 338     void profileSample() { return actualTC->profileSample(); }
 339
 340     // @todo: Do I need this?
 341     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 342
 343     void clearArchRegs() { actualTC->clearArchRegs(); }
 344
 345     //
 346     // New accessors for new decoder.
 347     //
 348     uint64_t readIntReg(int reg_idx)
 349     { return actualTC->readIntReg(reg_idx); }
 350
 351     FloatReg readFloatReg(int reg_idx)
 352     { return actualTC->readFloatReg(reg_idx); }
 353
 354     FloatRegBits readFloatRegBits(int reg_idx)
 355     { return actualTC->readFloatRegBits(reg_idx); }
 356
 357     void setIntReg(int reg_idx, uint64_t val)
 358     { actualTC->setIntReg(reg_idx, val); }
 359
 360     void setFloatReg(int reg_idx, FloatReg val)
 361     { actualTC->setFloatReg(reg_idx, val); }
 362
 363     void setFloatRegBits(int reg_idx, FloatRegBits val)
 364     { actualTC->setFloatRegBits(reg_idx, val); }
 365
 366     TheISA::PCState pcState() { return actualTC->pcState(); }
 367
 368     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 369
 370     Addr instAddr() { return actualTC->instAddr(); }
 371     Addr nextInstAddr() { return actualTC->nextInstAddr(); }
 372     MicroPC microPC() { return actualTC->microPC(); }
 373
 374     bool readPredicate() { return actualTC->readPredicate(); }
 375
 376     void setPredicate(bool val)
 377     { actualTC->setPredicate(val); }
 378
 379     MiscReg readMiscRegNoEffect(int misc_reg)
 380     { return actualTC->readMiscRegNoEffect(misc_reg); }
 381
 382     MiscReg readMiscReg(int misc_reg)
 383     { return actualTC->readMiscReg(misc_reg); }
 384
 385     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 386     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 387
 388     void setMiscReg(int misc_reg, const MiscReg &val)
 389     { return actualTC->setMiscReg(misc_reg, val); }
 390
 391     int flattenIntIndex(int reg)
 392     { return actualTC->flattenIntIndex(reg); }
 393
 394     int flattenFloatIndex(int reg)
 395     { return actualTC->flattenFloatIndex(reg); }
 396
 397     unsigned readStCondFailures()
 398     { return actualTC->readStCondFailures(); }
 399
 400     void setStCondFailures(unsigned sc_failures)
 401     { actualTC->setStCondFailures(sc_failures); }
 402
 403     // @todo: Fix this!
 404     bool misspeculating() { return actualTC->misspeculating(); }
 405
 406     void syscall(int64_t callnum)
 407     { actualTC->syscall(callnum); }
 408
 409     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 410 };
 411
 412 #endif