src/cpu/thread_context.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016-2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  */
  43
  44 #ifndef __CPU_THREAD_CONTEXT_HH__
  45 #define __CPU_THREAD_CONTEXT_HH__
  46
  47 #include <iostream>
  48 #include <string>
  49
  50 #include "arch/registers.hh"
  51 #include "arch/types.hh"
  52 #include "base/types.hh"
  53 #include "config/the_isa.hh"
  54 #include "cpu/pc_event.hh"
  55 #include "cpu/reg_class.hh"
  56
  57 // @todo: Figure out a more architecture independent way to obtain the ITB and
  58 // DTB pointers.
  59 namespace TheISA
  60 {
  61     class ISA;
  62     class Decoder;
  63 }
  64 class BaseCPU;
  65 class BaseTLB;
  66 class CheckerCPU;
  67 class Checkpoint;
  68 class EndQuiesceEvent;
  69 class PortProxy;
  70 class Process;
  71 class System;
  72 namespace Kernel {
  73     class Statistics;
  74 }
  75
  76 /**
  77  * ThreadContext is the external interface to all thread state for
  78  * anything outside of the CPU. It provides all accessor methods to
  79  * state that might be needed by external objects, ranging from
  80  * register values to things such as kernel stats. It is an abstract
  81  * base class; the CPU can create its own ThreadContext by
  82  * deriving from it.
  83  *
  84  * The ThreadContext is slightly different than the ExecContext.  The
  85  * ThreadContext provides access to an individual thread's state; an
  86  * ExecContext provides ISA access to the CPU (meaning it is
  87  * implicitly multithreaded on SMT systems).  Additionally the
  88  * ThreadState is an abstract class that exactly defines the
  89  * interface; the ExecContext is a more implicit interface that must
  90  * be implemented so that the ISA can access whatever state it needs.
  91  */
  92 class ThreadContext : public PCEventScope
  93 {
  94   protected:
  95     typedef TheISA::MachInst MachInst;
  96     using VecRegContainer = TheISA::VecRegContainer;
  97     using VecElem = TheISA::VecElem;
  98     using VecPredRegContainer = TheISA::VecPredRegContainer;
  99
 100   public:
 101
 102     enum Status
 103     {
 104         /// Running.  Instructions should be executed only when
 105         /// the context is in this state.
 106         Active,
 107
 108         /// Temporarily inactive.  Entered while waiting for
 109         /// synchronization, etc.
 110         Suspended,
 111
 112         /// Trying to exit and waiting for an event to completely exit.
 113         /// Entered when target executes an exit syscall.
 114         Halting,
 115
 116         /// Permanently shut down.  Entered when target executes
 117         /// m5exit pseudo-instruction.  When all contexts enter
 118         /// this state, the simulation will terminate.
 119         Halted
 120     };
 121
 122     virtual ~ThreadContext() { };
 123
 124     virtual BaseCPU *getCpuPtr() = 0;
 125
 126     virtual int cpuId() const = 0;
 127
 128     virtual uint32_t socketId() const = 0;
 129
 130     virtual int threadId() const = 0;
 131
 132     virtual void setThreadId(int id) = 0;
 133
 134     virtual ContextID contextId() const = 0;
 135
 136     virtual void setContextId(ContextID id) = 0;
 137
 138     virtual BaseTLB *getITBPtr() = 0;
 139
 140     virtual BaseTLB *getDTBPtr() = 0;
 141
 142     virtual CheckerCPU *getCheckerCpuPtr() = 0;
 143
 144     virtual TheISA::ISA *getIsaPtr() = 0;
 145
 146     virtual TheISA::Decoder *getDecoderPtr() = 0;
 147
 148     virtual System *getSystemPtr() = 0;
 149
 150     virtual ::Kernel::Statistics *getKernelStats() = 0;
 151
 152     virtual PortProxy &getPhysProxy() = 0;
 153
 154     virtual PortProxy &getVirtProxy() = 0;
 155
 156     /**
 157      * Initialise the physical and virtual port proxies and tie them to
 158      * the data port of the CPU.
 159      *
 160      * tc ThreadContext for the virtual-to-physical translation
 161      */
 162     virtual void initMemProxies(ThreadContext *tc) = 0;
 163
 164     virtual Process *getProcessPtr() = 0;
 165
 166     virtual void setProcessPtr(Process *p) = 0;
 167
 168     virtual Status status() const = 0;
 169
 170     virtual void setStatus(Status new_status) = 0;
 171
 172     /// Set the status to Active.
 173     virtual void activate() = 0;
 174
 175     /// Set the status to Suspended.
 176     virtual void suspend() = 0;
 177
 178     /// Set the status to Halted.
 179     virtual void halt() = 0;
 180
 181     /// Quiesce thread context
 182     void quiesce();
 183
 184     /// Quiesce, suspend, and schedule activate at resume
 185     void quiesceTick(Tick resume);
 186
 187     virtual void dumpFuncProfile() = 0;
 188
 189     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 190
 191     virtual void regStats(const std::string &name) = 0;
 192
 193     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 194
 195     virtual Tick nextInstEventCount();
 196     virtual void serviceInstCountEvents(Tick count);
 197     virtual void scheduleInstCountEvent(Event *event, Tick count);
 198     virtual void descheduleInstCountEvent(Event *event);
 199     virtual Tick getCurrentInstCount();
 200
 201     // Not necessarily the best location for these...
 202     // Having an extra function just to read these is obnoxious
 203     virtual Tick readLastActivate() = 0;
 204     virtual Tick readLastSuspend() = 0;
 205
 206     virtual void profileClear() = 0;
 207     virtual void profileSample() = 0;
 208
 209     virtual void copyArchRegs(ThreadContext *tc) = 0;
 210
 211     virtual void clearArchRegs() = 0;
 212
 213     //
 214     // New accessors for new decoder.
 215     //
 216     virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
 217
 218     virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
 219
 220     virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
 221     virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
 222
 223     /** Vector Register Lane Interfaces. */
 224     /** @{ */
 225     /** Reads source vector 8bit operand. */
 226     virtual ConstVecLane8
 227     readVec8BitLaneReg(const RegId& reg) const = 0;
 228
 229     /** Reads source vector 16bit operand. */
 230     virtual ConstVecLane16
 231     readVec16BitLaneReg(const RegId& reg) const = 0;
 232
 233     /** Reads source vector 32bit operand. */
 234     virtual ConstVecLane32
 235     readVec32BitLaneReg(const RegId& reg) const = 0;
 236
 237     /** Reads source vector 64bit operand. */
 238     virtual ConstVecLane64
 239     readVec64BitLaneReg(const RegId& reg) const = 0;
 240
 241     /** Write a lane of the destination vector register. */
 242     virtual void setVecLane(const RegId& reg,
 243             const LaneData<LaneSize::Byte>& val) = 0;
 244     virtual void setVecLane(const RegId& reg,
 245             const LaneData<LaneSize::TwoByte>& val) = 0;
 246     virtual void setVecLane(const RegId& reg,
 247             const LaneData<LaneSize::FourByte>& val) = 0;
 248     virtual void setVecLane(const RegId& reg,
 249             const LaneData<LaneSize::EightByte>& val) = 0;
 250     /** @} */
 251
 252     virtual const VecElem& readVecElem(const RegId& reg) const = 0;
 253
 254     virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
 255         const = 0;
 256     virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
 257
 258     virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
 259
 260     virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
 261
 262     virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
 263
 264     virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
 265
 266     virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
 267
 268     virtual void setVecPredReg(const RegId& reg,
 269                                const VecPredRegContainer& val) = 0;
 270
 271     virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
 272
 273     virtual TheISA::PCState pcState() const = 0;
 274
 275     virtual void pcState(const TheISA::PCState &val) = 0;
 276
 277     void
 278     setNPC(Addr val)
 279     {
 280         TheISA::PCState pc_state = pcState();
 281         pc_state.setNPC(val);
 282         pcState(pc_state);
 283     }
 284
 285     virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 286
 287     virtual Addr instAddr() const = 0;
 288
 289     virtual Addr nextInstAddr() const = 0;
 290
 291     virtual MicroPC microPC() const = 0;
 292
 293     virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
 294
 295     virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
 296
 297     virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
 298
 299     virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
 300
 301     virtual RegId flattenRegId(const RegId& regId) const = 0;
 302
 303     // Also not necessarily the best location for these two.  Hopefully will go
 304     // away once we decide upon where st cond failures goes.
 305     virtual unsigned readStCondFailures() const = 0;
 306
 307     virtual void setStCondFailures(unsigned sc_failures) = 0;
 308
 309     // Same with st cond failures.
 310     virtual Counter readFuncExeInst() const = 0;
 311
 312     virtual void syscall(int64_t callnum, Fault *fault) = 0;
 313
 314     // This function exits the thread context in the CPU and returns
 315     // 1 if the CPU has no more active threads (meaning it's OK to exit);
 316     // Used in syscall-emulation mode when a  thread calls the exit syscall.
 317     virtual int exit() { return 1; };
 318
 319     /** function to compare two thread contexts (for debugging) */
 320     static void compare(ThreadContext *one, ThreadContext *two);
 321
 322     /** @{ */
 323     /**
 324      * Flat register interfaces
 325      *
 326      * Some architectures have different registers visible in
 327      * different modes. Such architectures "flatten" a register (see
 328      * flattenRegId()) to map it into the
 329      * gem5 register file. This interface provides a flat interface to
 330      * the underlying register file, which allows for example
 331      * serialization code to access all registers.
 332      */
 333
 334     virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
 335     virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
 336
 337     virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
 338     virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
 339
 340     virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
 341     virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
 342     virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
 343
 344     virtual const VecElem& readVecElemFlat(RegIndex idx,
 345                                            const ElemIndex& elemIdx) const = 0;
 346     virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
 347                                 const VecElem& val) = 0;
 348
 349     virtual const VecPredRegContainer &
 350         readVecPredRegFlat(RegIndex idx) const = 0;
 351     virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
 352     virtual void setVecPredRegFlat(RegIndex idx,
 353                                    const VecPredRegContainer& val) = 0;
 354
 355     virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
 356     virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
 357     /** @} */
 358
 359 };
 360
 361 /** @{ */
 362 /**
 363  * Thread context serialization helpers
 364  *
 365  * These helper functions provide a way to the data in a
 366  * ThreadContext. They are provided as separate helper function since
 367  * implementing them as members of the ThreadContext interface would
 368  * be confusing when the ThreadContext is exported via a proxy.
 369  */
 370
 371 void serialize(const ThreadContext &tc, CheckpointOut &cp);
 372 void unserialize(ThreadContext &tc, CheckpointIn &cp);
 373
 374 /** @} */
 375
 376
 377 /**
 378  * Copy state between thread contexts in preparation for CPU handover.
 379  *
 380  * @note This method modifies the old thread contexts as well as the
 381  * new thread context. The old thread context will have its quiesce
 382  * event descheduled if it is scheduled and its status set to halted.
 383  *
 384  * @param new_tc Destination ThreadContext.
 385  * @param old_tc Source ThreadContext.
 386  */
 387 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
 388
 389 #endif