src/cpu/thread_state.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "cpu/thread_state.hh"
  30
  31 #include "base/output.hh"
  32 #include "cpu/base.hh"
  33 #include "mem/port.hh"
  34 #include "mem/port_proxy.hh"
  35 #include "mem/se_translating_port_proxy.hh"
  36 #include "mem/translating_port_proxy.hh"
  37 #include "sim/full_system.hh"
  38 #include "sim/serialize.hh"
  39 #include "sim/system.hh"
  40
  41 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
  42     : numInst(0), numOp(0), threadStats(cpu, this),
  43       numLoad(0), startNumLoad(0),
  44       _status(ThreadContext::Halted), baseCpu(cpu),
  45       _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
  46       process(_process), physProxy(NULL), virtProxy(NULL),
  47       funcExeInst(0), storeCondFailures(0)
  48 {
  49 }
  50
  51 ThreadState::~ThreadState()
  52 {
  53     if (physProxy != NULL)
  54         delete physProxy;
  55     if (virtProxy != NULL)
  56         delete virtProxy;
  57 }
  58
  59 void
  60 ThreadState::serialize(CheckpointOut &cp) const
  61 {
  62     SERIALIZE_ENUM(_status);
  63     // thread_num and cpu_id are deterministic from the config
  64     SERIALIZE_SCALAR(funcExeInst);
  65
  66     if (!FullSystem)
  67         return;
  68 }
  69
  70 void
  71 ThreadState::unserialize(CheckpointIn &cp)
  72 {
  73
  74     UNSERIALIZE_ENUM(_status);
  75     // thread_num and cpu_id are deterministic from the config
  76     UNSERIALIZE_SCALAR(funcExeInst);
  77
  78     if (!FullSystem)
  79         return;
  80 }
  81
  82 void
  83 ThreadState::initMemProxies(ThreadContext *tc)
  84 {
  85     // The port proxies only refer to the data port on the CPU side
  86     // and can safely be done at init() time even if the CPU is not
  87     // connected, i.e. when restoring from a checkpoint and later
  88     // switching the CPU in.
  89     if (FullSystem) {
  90         assert(physProxy == NULL);
  91         // This cannot be done in the constructor as the thread state
  92         // itself is created in the base cpu constructor and the
  93         // getSendFunctional is a virtual function
  94         physProxy = new PortProxy(baseCpu->getSendFunctional(),
  95                                   baseCpu->cacheLineSize());
  96
  97         assert(virtProxy == NULL);
  98         virtProxy = new TranslatingPortProxy(tc);
  99     } else {
 100         assert(virtProxy == NULL);
 101         virtProxy = new SETranslatingPortProxy(
 102                 tc, SETranslatingPortProxy::NextPage);
 103     }
 104 }
 105
 106 PortProxy &
 107 ThreadState::getPhysProxy()
 108 {
 109     assert(FullSystem);
 110     assert(physProxy != NULL);
 111     return *physProxy;
 112 }
 113
 114 PortProxy &
 115 ThreadState::getVirtProxy()
 116 {
 117     assert(virtProxy != NULL);
 118     return *virtProxy;
 119 }
 120
 121 ThreadState::ThreadStateStats::ThreadStateStats(BaseCPU *cpu,
 122                                                 ThreadState *thread)
 123       : Stats::Group(cpu, csprintf("thread%i", thread->threadId()).c_str()),
 124       ADD_STAT(numInsts, "Number of Instructions committed"),
 125       ADD_STAT(numOps, "Number of Ops committed"),
 126       ADD_STAT(numMemRefs, "Number of Memory References")
 127 {
 128
 129 }