src/cpu/thread_state.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "base/output.hh"
  32 #include "cpu/base.hh"
  33 #include "cpu/profile.hh"
  34 #include "cpu/thread_state.hh"
  35 #include "mem/port.hh"
  36 #include "mem/translating_port.hh"
  37 #include "sim/serialize.hh"
  38
  39 #if FULL_SYSTEM
  40 #include "arch/kernel_stats.hh"
  41 #include "cpu/quiesce_event.hh"
  42 #include "mem/vport.hh"
  43 #endif
  44
  45 #if FULL_SYSTEM
  46 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
  47 #else
  48 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
  49 #endif
  50     : numInst(0), numLoad(0), _status(ThreadContext::Halted),
  51       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
  52 #if FULL_SYSTEM
  53       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
  54       kernelStats(NULL), physPort(NULL), virtPort(NULL),
  55 #else
  56       port(NULL), process(_process),
  57 #endif
  58       funcExeInst(0), storeCondFailures(0)
  59 {
  60 }
  61
  62 ThreadState::~ThreadState()
  63 {
  64 #if !FULL_SYSTEM
  65     if (port) {
  66         delete port->getPeer();
  67         delete port;
  68     }
  69 #endif
  70 }
  71
  72 void
  73 ThreadState::serialize(std::ostream &os)
  74 {
  75     SERIALIZE_ENUM(_status);
  76     // thread_num and cpu_id are deterministic from the config
  77     SERIALIZE_SCALAR(funcExeInst);
  78
  79 #if FULL_SYSTEM
  80     Tick quiesceEndTick = 0;
  81     if (quiesceEvent->scheduled())
  82         quiesceEndTick = quiesceEvent->when();
  83     SERIALIZE_SCALAR(quiesceEndTick);
  84     if (kernelStats)
  85         kernelStats->serialize(os);
  86 #endif
  87 }
  88
  89 void
  90 ThreadState::unserialize(Checkpoint *cp, const std::string &section)
  91 {
  92
  93     UNSERIALIZE_ENUM(_status);
  94     // thread_num and cpu_id are deterministic from the config
  95     UNSERIALIZE_SCALAR(funcExeInst);
  96
  97 #if FULL_SYSTEM
  98     Tick quiesceEndTick;
  99     UNSERIALIZE_SCALAR(quiesceEndTick);
 100     if (quiesceEndTick)
 101         baseCpu->schedule(quiesceEvent, quiesceEndTick);
 102     if (kernelStats)
 103         kernelStats->unserialize(cp, section);
 104 #endif
 105 }
 106
 107 #if FULL_SYSTEM
 108 void
 109 ThreadState::connectMemPorts(ThreadContext *tc)
 110 {
 111     connectPhysPort();
 112     connectVirtPort(tc);
 113 }
 114
 115 void
 116 ThreadState::connectPhysPort()
 117 {
 118     // @todo: For now this disregards any older port that may have
 119     // already existed.  Fix this memory leak once the bus port IDs
 120     // for functional ports is resolved.
 121     if (physPort)
 122         physPort->removeConn();
 123     else
 124         physPort = new FunctionalPort(csprintf("%s-%d-funcport",
 125                                            baseCpu->name(), _threadId));
 126     connectToMemFunc(physPort);
 127 }
 128
 129 void
 130 ThreadState::connectVirtPort(ThreadContext *tc)
 131 {
 132     // @todo: For now this disregards any older port that may have
 133     // already existed.  Fix this memory leak once the bus port IDs
 134     // for functional ports is resolved.
 135     if (virtPort)
 136         virtPort->removeConn();
 137     else
 138         virtPort = new VirtualPort(csprintf("%s-%d-vport",
 139                                         baseCpu->name(), _threadId), tc);
 140     connectToMemFunc(virtPort);
 141 }
 142
 143 void
 144 ThreadState::profileClear()
 145 {
 146     if (profile)
 147         profile->clear();
 148 }
 149
 150 void
 151 ThreadState::profileSample()
 152 {
 153     if (profile)
 154         profile->sample(profileNode, profilePC);
 155 }
 156
 157 #else
 158 TranslatingPort *
 159 ThreadState::getMemPort()
 160 {
 161     if (port != NULL)
 162         return port;
 163
 164     /* Use this port to for syscall emulation writes to memory. */
 165     port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
 166                                process, TranslatingPort::NextPage);
 167
 168     connectToMemFunc(port);
 169
 170     return port;
 171 }
 172 #endif
 173
 174 void
 175 ThreadState::connectToMemFunc(Port *port)
 176 {
 177     Port *dcache_port, *func_mem_port;
 178
 179     dcache_port = baseCpu->getPort("dcache_port");
 180     assert(dcache_port != NULL);
 181
 182     MemObject *mem_object = dcache_port->getPeer()->getOwner();
 183     assert(mem_object != NULL);
 184
 185     func_mem_port = mem_object->getPort("functional");
 186     assert(func_mem_port != NULL);
 187
 188     func_mem_port->setPeer(port);
 189     port->setPeer(func_mem_port);
 190 }