src/cpu/thread_state.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "arch/kernel_stats.hh"
  32 #include "base/output.hh"
  33 #include "cpu/base.hh"
  34 #include "cpu/profile.hh"
  35 #include "cpu/quiesce_event.hh"
  36 #include "cpu/thread_state.hh"
  37 #include "mem/port.hh"
  38 #include "mem/translating_port.hh"
  39 #include "mem/vport.hh"
  40 #include "sim/full_system.hh"
  41 #include "sim/serialize.hh"
  42
  43 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
  44     : numInst(0), numLoad(0), _status(ThreadContext::Halted),
  45       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
  46       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
  47       kernelStats(NULL), process(_process), port(NULL), virtPort(NULL),
  48       physPort(NULL), funcExeInst(0), storeCondFailures(0)
  49 {
  50 }
  51
  52 ThreadState::~ThreadState()
  53 {
  54     if (port) {
  55         delete port->getPeer();
  56         delete port;
  57     }
  58 }
  59
  60 void
  61 ThreadState::serialize(std::ostream &os)
  62 {
  63     SERIALIZE_ENUM(_status);
  64     // thread_num and cpu_id are deterministic from the config
  65     SERIALIZE_SCALAR(funcExeInst);
  66
  67     if (FullSystem) {
  68         Tick quiesceEndTick = 0;
  69         if (quiesceEvent->scheduled())
  70             quiesceEndTick = quiesceEvent->when();
  71         SERIALIZE_SCALAR(quiesceEndTick);
  72         if (kernelStats)
  73             kernelStats->serialize(os);
  74     }
  75 }
  76
  77 void
  78 ThreadState::unserialize(Checkpoint *cp, const std::string &section)
  79 {
  80
  81     UNSERIALIZE_ENUM(_status);
  82     // thread_num and cpu_id are deterministic from the config
  83     UNSERIALIZE_SCALAR(funcExeInst);
  84
  85     if (FullSystem) {
  86         Tick quiesceEndTick;
  87         UNSERIALIZE_SCALAR(quiesceEndTick);
  88         if (quiesceEndTick)
  89             baseCpu->schedule(quiesceEvent, quiesceEndTick);
  90         if (kernelStats)
  91             kernelStats->unserialize(cp, section);
  92     }
  93 }
  94
  95 void
  96 ThreadState::connectPhysPort()
  97 {
  98     // @todo: For now this disregards any older port that may have
  99     // already existed.  Fix this memory leak once the bus port IDs
 100     // for functional ports is resolved.
 101     if (physPort)
 102         physPort->removeConn();
 103     else
 104         physPort = new FunctionalPort(csprintf("%s-%d-funcport",
 105                                            baseCpu->name(), _threadId));
 106     connectToMemFunc(physPort);
 107 }
 108
 109 void
 110 ThreadState::connectVirtPort(ThreadContext *tc)
 111 {
 112     // @todo: For now this disregards any older port that may have
 113     // already existed.  Fix this memory leak once the bus port IDs
 114     // for functional ports is resolved.
 115     if (virtPort)
 116         virtPort->removeConn();
 117     else
 118         virtPort = new VirtualPort(csprintf("%s-%d-vport",
 119                                         baseCpu->name(), _threadId), tc);
 120     connectToMemFunc(virtPort);
 121 }
 122
 123 void
 124 ThreadState::connectMemPorts(ThreadContext *tc)
 125 {
 126     connectPhysPort();
 127     connectVirtPort(tc);
 128 }
 129
 130 void
 131 ThreadState::profileClear()
 132 {
 133     if (profile)
 134         profile->clear();
 135 }
 136
 137 void
 138 ThreadState::profileSample()
 139 {
 140     if (profile)
 141         profile->sample(profileNode, profilePC);
 142 }
 143
 144 TranslatingPort *
 145 ThreadState::getMemPort()
 146 {
 147     if (port != NULL)
 148         return port;
 149
 150     /* Use this port to for syscall emulation writes to memory. */
 151     port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(),
 152                                _threadId), process, TranslatingPort::NextPage);
 153
 154     connectToMemFunc(port);
 155
 156     return port;
 157 }
 158
 159 void
 160 ThreadState::connectToMemFunc(Port *port)
 161 {
 162     Port *dcache_port, *func_mem_port;
 163
 164     dcache_port = baseCpu->getPort("dcache_port");
 165     assert(dcache_port != NULL);
 166
 167     MemObject *mem_object = dcache_port->getPeer()->getOwner();
 168     assert(mem_object != NULL);
 169
 170     func_mem_port = mem_object->getPort("functional");
 171     assert(func_mem_port != NULL);
 172
 173     func_mem_port->setPeer(port);
 174     port->setPeer(func_mem_port);
 175 }