Started implementing microcode.
[gem5.git] / src / cpu / thread_state.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #ifndef __CPU_THREAD_STATE_HH__
32 #define __CPU_THREAD_STATE_HH__
33
34 #include "arch/types.hh"
35 #include "cpu/profile.hh"
36 #include "cpu/thread_context.hh"
37
38 #if !FULL_SYSTEM
39 #include "mem/mem_object.hh"
40 #include "mem/translating_port.hh"
41 #include "sim/process.hh"
42 #endif
43
44 #if FULL_SYSTEM
45 class EndQuiesceEvent;
46 class FunctionProfile;
47 class ProfileNode;
48 namespace Kernel {
49 class Statistics;
50 };
51 #endif
52
53 class Checkpoint;
54
55 /**
56 * Struct for holding general thread state that is needed across CPU
57 * models. This includes things such as pointers to the process,
58 * memory, quiesce events, and certain stats. This can be expanded
59 * to hold more thread-specific stats within it.
60 */
61 struct ThreadState {
62 typedef ThreadContext::Status Status;
63
64 #if FULL_SYSTEM
65 ThreadState(int _cpuId, int _tid);
66 #else
67 ThreadState(int _cpuId, int _tid, Process *_process,
68 short _asid, MemObject *mem);
69 #endif
70
71 void serialize(std::ostream &os);
72
73 void unserialize(Checkpoint *cp, const std::string &section);
74
75 void setCpuId(int id) { cpuId = id; }
76
77 int readCpuId() { return cpuId; }
78
79 void setTid(int id) { tid = id; }
80
81 int readTid() { return tid; }
82
83 Tick readLastActivate() { return lastActivate; }
84
85 Tick readLastSuspend() { return lastSuspend; }
86
87 #if FULL_SYSTEM
88 void dumpFuncProfile();
89
90 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
91
92 void profileClear();
93
94 void profileSample();
95
96 Kernel::Statistics *getKernelStats() { return kernelStats; }
97
98 FunctionalPort *getPhysPort() { return physPort; }
99
100 void setPhysPort(FunctionalPort *port) { physPort = port; }
101
102 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
103
104 void setVirtPort(VirtualPort *port) { virtPort = port; }
105 #else
106 Process *getProcessPtr() { return process; }
107
108 TranslatingPort *getMemPort() { return port; }
109
110 void setMemPort(TranslatingPort *_port) { port = _port; }
111
112 int getInstAsid() { return asid; }
113 int getDataAsid() { return asid; }
114 #endif
115
116 /** Sets the current instruction being committed. */
117 void setInst(TheISA::MachInst _inst) { inst = _inst; }
118
119 /** Returns the current instruction being committed. */
120 TheISA::MachInst getInst() { return inst; }
121
122 /** Reads the number of instructions functionally executed and
123 * committed.
124 */
125 Counter readFuncExeInst() { return funcExeInst; }
126
127 /** Sets the total number of instructions functionally executed
128 * and committed.
129 */
130 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
131
132 /** Returns the status of this thread. */
133 Status status() const { return _status; }
134
135 /** Sets the status of this thread. */
136 void setStatus(Status new_status) { _status = new_status; }
137
138 /** Number of instructions committed. */
139 Counter numInst;
140 /** Stat for number instructions committed. */
141 Stats::Scalar<> numInsts;
142 /** Stat for number of memory references. */
143 Stats::Scalar<> numMemRefs;
144
145 /** Number of simulated loads, used for tracking events based on
146 * the number of loads committed.
147 */
148 Counter numLoad;
149
150 /** The number of simulated loads committed prior to this run. */
151 Counter startNumLoad;
152
153 protected:
154 ThreadContext::Status _status;
155
156 // ID of this context w.r.t. the System or Process object to which
157 // it belongs. For full-system mode, this is the system CPU ID.
158 int cpuId;
159
160 // Index of hardware thread context on the CPU that this represents.
161 int tid;
162
163 public:
164 /** Last time activate was called on this thread. */
165 Tick lastActivate;
166
167 /** Last time suspend was called on this thread. */
168 Tick lastSuspend;
169
170 #if FULL_SYSTEM
171 public:
172 FunctionProfile *profile;
173 ProfileNode *profileNode;
174 Addr profilePC;
175 EndQuiesceEvent *quiesceEvent;
176
177 Kernel::Statistics *kernelStats;
178 protected:
179 /** A functional port outgoing only for functional accesses to physical
180 * addresses.*/
181 FunctionalPort *physPort;
182
183 /** A functional port, outgoing only, for functional accesse to virtual
184 * addresses. That doen't require execution context information */
185 VirtualPort *virtPort;
186 #else
187 TranslatingPort *port;
188
189 Process *process;
190
191 // Address space ID. Note that this is used for TIMING cache
192 // simulation only; all functional memory accesses should use
193 // one of the FunctionalMemory pointers above.
194 short asid;
195
196 #endif
197
198 /** Current instruction the thread is committing. Only set and
199 * used for DTB faults currently.
200 */
201 TheISA::MachInst inst;
202
203 /** The current microcode pc for the currently executing macro
204 * operation.
205 */
206 MicroPC microPC;
207
208 /** The next microcode pc for the currently executing macro
209 * operation.
210 */
211 MicroPC nextMicroPC;
212
213 public:
214 /**
215 * Temporary storage to pass the source address from copy_load to
216 * copy_store.
217 * @todo Remove this temporary when we have a better way to do it.
218 */
219 Addr copySrcAddr;
220 /**
221 * Temp storage for the physical source address of a copy.
222 * @todo Remove this temporary when we have a better way to do it.
223 */
224 Addr copySrcPhysAddr;
225
226 /*
227 * number of executed instructions, for matching with syscall trace
228 * points in EIO files.
229 */
230 Counter funcExeInst;
231
232 //
233 // Count failed store conditionals so we can warn of apparent
234 // application deadlock situations.
235 unsigned storeCondFailures;
236 };
237
238 #endif // __CPU_THREAD_STATE_HH__