src/cpu/thread_state.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_THREAD_STATE_HH__
  30 #define __CPU_THREAD_STATE_HH__
  31
  32 #include "arch/isa_traits.hh"
  33 #include "cpu/thread_context.hh"
  34
  35 #if !FULL_SYSTEM
  36 #include "mem/mem_object.hh"
  37 #include "mem/translating_port.hh"
  38 #include "sim/process.hh"
  39 #endif
  40
  41 #if FULL_SYSTEM
  42 class EndQuiesceEvent;
  43 class FunctionProfile;
  44 class ProfileNode;
  45 namespace Kernel {
  46     class Statistics;
  47 };
  48 #endif
  49
  50 /**
  51  *  Struct for holding general thread state that is needed across CPU
  52  *  models.  This includes things such as pointers to the process,
  53  *  memory, quiesce events, and certain stats.  This can be expanded
  54  *  to hold more thread-specific stats within it.
  55  */
  56 struct ThreadState {
  57     typedef ThreadContext::Status Status;
  58
  59 #if FULL_SYSTEM
  60     ThreadState(int _cpuId, int _tid);
  61 #else
  62     ThreadState(int _cpuId, int _tid, MemObject *mem,
  63                 Process *_process, short _asid);
  64 #endif
  65
  66     void setCpuId(int id) { cpuId = id; }
  67
  68     int readCpuId() { return cpuId; }
  69
  70     void setTid(int id) { tid = id; }
  71
  72     int readTid() { return tid; }
  73
  74     Tick readLastActivate() { return lastActivate; }
  75
  76     Tick readLastSuspend() { return lastSuspend; }
  77
  78 #if FULL_SYSTEM
  79     void dumpFuncProfile();
  80
  81     EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
  82
  83     void profileClear();
  84
  85     void profileSample();
  86
  87     Kernel::Statistics *getKernelStats() { return kernelStats; }
  88
  89     void setPhysPort(FunctionalPort *port) { physPort = port; }
  90
  91     void setVirtPort(VirtualPort *port) { virtPort = port; }
  92 #else
  93     Process *getProcessPtr() { return process; }
  94
  95     TranslatingPort *getMemPort() { return port; }
  96
  97     void setMemPort(TranslatingPort *_port) { port = _port; }
  98
  99     int getInstAsid() { return asid; }
 100     int getDataAsid() { return asid; }
 101 #endif
 102
 103     /** Sets the current instruction being committed. */
 104     void setInst(TheISA::MachInst _inst) { inst = _inst; }
 105
 106     /** Returns the current instruction being committed. */
 107     TheISA::MachInst getInst() { return inst; }
 108
 109     /** Reads the number of instructions functionally executed and
 110      * committed.
 111      */
 112     Counter readFuncExeInst() { return funcExeInst; }
 113
 114     /** Sets the total number of instructions functionally executed
 115      * and committed.
 116      */
 117     void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
 118
 119     /** Returns the status of this thread. */
 120     Status status() const { return _status; }
 121
 122     /** Sets the status of this thread. */
 123     void setStatus(Status new_status) { _status = new_status; }
 124
 125     /** Number of instructions committed. */
 126     Counter numInst;
 127     /** Stat for number instructions committed. */
 128     Stats::Scalar<> numInsts;
 129     /** Stat for number of memory references. */
 130     Stats::Scalar<> numMemRefs;
 131
 132     /** Number of simulated loads, used for tracking events based on
 133      * the number of loads committed.
 134      */
 135     Counter numLoad;
 136
 137     /** The number of simulated loads committed prior to this run. */
 138     Counter startNumLoad;
 139
 140   protected:
 141     ThreadContext::Status _status;
 142
 143     // ID of this context w.r.t. the System or Process object to which
 144     // it belongs.  For full-system mode, this is the system CPU ID.
 145     int cpuId;
 146
 147     // Index of hardware thread context on the CPU that this represents.
 148     int tid;
 149
 150     /** Last time activate was called on this thread. */
 151     Tick lastActivate;
 152
 153     /** Last time suspend was called on this thread. */
 154     Tick lastSuspend;
 155
 156 #if FULL_SYSTEM
 157   public:
 158     FunctionProfile *profile;
 159     ProfileNode *profileNode;
 160     Addr profilePC;
 161     EndQuiesceEvent *quiesceEvent;
 162
 163     Kernel::Statistics *kernelStats;
 164   protected:
 165     /** A functional port outgoing only for functional accesses to physical
 166      * addresses.*/
 167     FunctionalPort *physPort;
 168
 169     /** A functional port, outgoing only, for functional accesse to virtual
 170      * addresses. That doen't require execution context information */
 171     VirtualPort *virtPort;
 172 #else
 173     TranslatingPort *port;
 174
 175     Process *process;
 176
 177     // Address space ID.  Note that this is used for TIMING cache
 178     // simulation only; all functional memory accesses should use
 179     // one of the FunctionalMemory pointers above.
 180     short asid;
 181 #endif
 182
 183     /** Current instruction the thread is committing.  Only set and
 184      * used for DTB faults currently.
 185      */
 186     TheISA::MachInst inst;
 187
 188     /**
 189      * Temporary storage to pass the source address from copy_load to
 190      * copy_store.
 191      * @todo Remove this temporary when we have a better way to do it.
 192      */
 193     Addr copySrcAddr;
 194     /**
 195      * Temp storage for the physical source address of a copy.
 196      * @todo Remove this temporary when we have a better way to do it.
 197      */
 198     Addr copySrcPhysAddr;
 199
 200   public:
 201     /*
 202      * number of executed instructions, for matching with syscall trace
 203      * points in EIO files.
 204      */
 205     Counter funcExeInst;
 206
 207     //
 208     // Count failed store conditionals so we can warn of apparent
 209     // application deadlock situations.
 210     unsigned storeCondFailures;
 211 };
 212
 213 #endif // __CPU_THREAD_STATE_HH__