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36 from m5
.params
import *
37 from m5
.objects
.BaseCPU
import BaseCPU
39 class TraceCPU(BaseCPU
):
40 """Trace CPU model which replays traces generated in a prior simulation
41 using DerivO3CPU or its derived classes. It interfaces with L1 caches.
44 cxx_header
= "cpu/trace/trace_cpu.hh"
51 def require_caches(cls
):
54 def addPMU(self
, pmu
= None):
58 def support_take_over(cls
):
61 instTraceFile
= Param
.String("", "Instruction trace file")
62 dataTraceFile
= Param
.String("", "Data dependency trace file")
63 sizeStoreBuffer
= Param
.Unsigned(16, "Number of entries in the store "\
65 sizeLoadBuffer
= Param
.Unsigned(16, "Number of entries in the load buffer")
66 sizeROB
= Param
.Unsigned(40, "Number of entries in the re-order buffer")
68 # Frequency multiplier used to effectively scale the Trace CPU frequency
69 # either up or down. Note that the Trace CPU's clock domain must also be
70 # changed when frequency is scaled. A default value of 1.0 means the same
71 # frequency as was used for generating the traces.
72 freqMultiplier
= Param
.Float(1.0, "Multiplier scale the Trace CPU "\
73 "frequency up or down")
75 # Enable exiting when any one Trace CPU completes execution which is set to
77 enableEarlyExit
= Param
.Bool(False, "Exit when any one Trace CPU "\
78 "completes execution")
80 # If progress msg interval is set to a non-zero value, it is treated as
81 # the interval of committed instructions at which an info message is
83 progressMsgInterval
= Param
.Unsigned(0, "Interval of committed "\
84 "instructions at which to print a"\