2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
33 * Declaration of a memory trace CPU object. Uses a memory trace to drive the
34 * provided memory hierarchy.
37 #include <algorithm> // For min
39 #include "cpu/trace/trace_cpu.hh"
40 #include "cpu/trace/reader/mem_trace_reader.hh"
41 #include "mem/base_mem.hh" // For PARAM constructor
42 #include "mem/mem_interface.hh"
43 #include "sim/builder.hh"
44 #include "sim/sim_events.hh"
48 TraceCPU::TraceCPU(const string
&name
,
49 MemInterface
*icache_interface
,
50 MemInterface
*dcache_interface
,
51 MemTraceReader
*data_trace
)
52 : SimObject(name
), icacheInterface(icache_interface
),
53 dcacheInterface(dcache_interface
),
54 dataTrace(data_trace
), outstandingRequests(0), tickEvent(this)
56 assert(dcacheInterface
);
57 nextCycle
= dataTrace
->getNextReq(nextReq
);
58 tickEvent
.schedule(0);
64 assert(outstandingRequests
>= 0);
65 assert(outstandingRequests
< 1000);
69 while (nextReq
&& curTick
>= nextCycle
) {
70 assert(nextReq
->thread_num
< 4 && "Not enough threads");
71 if (nextReq
->isInstRead() && icacheInterface
) {
72 if (icacheInterface
->isBlocked())
75 nextReq
->time
= curTick
;
76 if (nextReq
->cmd
== Squash
) {
77 icacheInterface
->squash(nextReq
->asid
);
80 if (icacheInterface
->doEvents()) {
81 nextReq
->completionEvent
=
82 new TraceCompleteEvent(nextReq
, this);
83 icacheInterface
->access(nextReq
);
85 icacheInterface
->access(nextReq
);
86 completeRequest(nextReq
);
90 if (dcacheInterface
->isBlocked())
94 nextReq
->time
= curTick
;
95 if (dcacheInterface
->doEvents()) {
96 nextReq
->completionEvent
=
97 new TraceCompleteEvent(nextReq
, this);
98 dcacheInterface
->access(nextReq
);
100 dcacheInterface
->access(nextReq
);
101 completeRequest(nextReq
);
105 nextCycle
= dataTrace
->getNextReq(nextReq
);
109 // No more requests to send. Finish trailing events and exit.
110 if (mainEventQueue
.empty()) {
111 exitSimLoop("end of memory trace reached");
113 tickEvent
.schedule(mainEventQueue
.nextEventTime() + cycles(1));
116 tickEvent
.schedule(max(curTick
+ cycles(1), nextCycle
));
121 TraceCPU::completeRequest(MemReqPtr
& req
)
126 TraceCompleteEvent::process()
128 tester
->completeRequest(req
);
132 TraceCompleteEvent::description()
134 return "trace access complete";
137 TraceCPU::TickEvent::TickEvent(TraceCPU
*c
)
138 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
143 TraceCPU::TickEvent::process()
149 TraceCPU::TickEvent::description()
151 return "TraceCPU tick event";
156 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
158 SimObjectParam
<BaseMem
*> icache
;
159 SimObjectParam
<BaseMem
*> dcache
;
160 SimObjectParam
<MemTraceReader
*> data_trace
;
162 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
164 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
166 INIT_PARAM_DFLT(icache
, "instruction cache", NULL
),
167 INIT_PARAM_DFLT(dcache
, "data cache", NULL
),
168 INIT_PARAM_DFLT(data_trace
, "data trace", NULL
)
170 END_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
172 CREATE_SIM_OBJECT(TraceCPU
)
174 return new TraceCPU(getInstanceName(),
175 (icache
) ? icache
->getInterface() : NULL
,
176 (dcache
) ? dcache
->getInterface() : NULL
,
180 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU
)