A possible implementation of a multiplexed bus.
[gem5.git] / src / cpu / trace / trace_cpu.hh
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31 /**
32 * @file
33 * Declaration of a memory trace CPU object. Uses a memory trace to drive the
34 * provided memory hierarchy.
35 */
36
37 #ifndef __CPU_TRACE_TRACE_CPU_HH__
38 #define __CPU_TRACE_TRACE_CPU_HH__
39
40 #include <string>
41
42 #include "mem/mem_req.hh" // for MemReqPtr
43 #include "sim/eventq.hh" // for Event
44 #include "sim/sim_object.hh"
45
46 // Forward declaration.
47 class MemInterface;
48 class MemTraceReader;
49
50 /**
51 * A cpu object for running memory traces through a memory hierarchy.
52 */
53 class TraceCPU : public SimObject
54 {
55 private:
56 /** Interface for instruction trace requests, if any. */
57 MemInterface *icacheInterface;
58 /** Interface for data trace requests, if any. */
59 MemInterface *dcacheInterface;
60
61 /** Data reference trace. */
62 MemTraceReader *dataTrace;
63
64 /** Number of outstanding requests. */
65 int outstandingRequests;
66
67 /** Cycle of the next request, 0 if not available. */
68 Tick nextCycle;
69
70 /** Next request. */
71 MemReqPtr nextReq;
72
73 /**
74 * Event to call the TraceCPU::tick
75 */
76 class TickEvent : public Event
77 {
78 private:
79 /** The associated CPU */
80 TraceCPU *cpu;
81
82 public:
83 /**
84 * Construct this event;
85 */
86 TickEvent(TraceCPU *c);
87
88 /**
89 * Call the tick function.
90 */
91 void process();
92
93 /**
94 * Return a string description of this event.
95 */
96 const char *description();
97 };
98
99 TickEvent tickEvent;
100
101 public:
102 /**
103 * Construct a TraceCPU object.
104 */
105 TraceCPU(const std::string &name,
106 MemInterface *icache_interface,
107 MemInterface *dcache_interface,
108 MemTraceReader *data_trace);
109
110 inline Tick cycles(int numCycles) { return numCycles; }
111
112 /**
113 * Perform all the accesses for one cycle.
114 */
115 void tick();
116
117 /**
118 * Handle a completed memory request.
119 */
120 void completeRequest(MemReqPtr &req);
121 };
122
123 class TraceCompleteEvent : public Event
124 {
125 MemReqPtr req;
126 TraceCPU *tester;
127
128 public:
129
130 TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester)
131 : Event(&mainEventQueue), req(_req), tester(_tester)
132 {
133 setFlags(AutoDelete);
134 }
135
136 void process();
137
138 virtual const char *description();
139 };
140
141 #endif // __CPU_TRACE_TRACE_CPU_HH__
142