cpu: Delete authors lists from the cpu directory.
[gem5.git] / src / cpu / utils.hh
1 /*
2 * Copyright (c) 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef __CPU_UTILS_HH__
39 #define __CPU_UTILS_HH__
40
41 #include "base/types.hh"
42
43 /**
44 * Calculates the offset of a given address wrt aligned fixed-size blocks.
45 * @param addr Input address.
46 * @param block_size Block size in bytes.
47 * @return Offset of the given address in bytes.
48 */
49 inline Addr
50 addrBlockOffset(Addr addr, Addr block_size)
51 {
52 return addr & (block_size - 1);
53 }
54
55 /**
56 * Returns the address of the closest aligned fixed-size block to the given
57 * address.
58 * @param addr Input address.
59 * @param block_size Block size in bytes.
60 * @return Address of the closest aligned block.
61 */
62 inline Addr
63 addrBlockAlign(Addr addr, Addr block_size)
64 {
65 return addr & ~(block_size - 1);
66 }
67
68 /**
69 * Returns true if the given memory access (address, size) needs to be
70 * fragmented across aligned fixed-size blocks.
71 * @param addr Address of the memory access.
72 * @param size Size of the memory access.
73 * @param block_size Block size in bytes.
74 * @return True if the memory access needs to be fragmented.
75 */
76 inline bool
77 transferNeedsBurst(Addr addr, unsigned int size, unsigned int block_size)
78 {
79 return (addrBlockOffset(addr, block_size) + size) > block_size;
80 }
81
82 /**
83 * Test if there is any active element in an enablement range.
84 */
85 inline bool
86 isAnyActiveElement(const std::vector<bool>::const_iterator& it_start,
87 const std::vector<bool>::const_iterator& it_end)
88 {
89 auto it_tmp = it_start;
90 for (;it_tmp != it_end && !(*it_tmp); ++it_tmp);
91 return (it_tmp != it_end);
92 }
93
94 #endif // __CPU_UTILS_HH__