ISA: Simplify various implementations of completeAcc.
[gem5.git] / src / dev / CopyEngine.py
1 # Copyright (c) 2008 The Regents of The University of Michigan
2 # All rights reserved.
3 #
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
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8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
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11 # neither the name of the copyright holders nor the names of its
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13 # this software without specific prior written permission.
14 #
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #
27 # Authors: Ali Saidi
28
29 from m5.SimObject import SimObject
30 from m5.params import *
31 from m5.proxy import *
32 from Pci import PciDevice
33
34 class CopyEngine(PciDevice):
35 type = 'CopyEngine'
36 VendorID = 0x8086
37 DeviceID = 0x1a38
38 Revision = 0xA2 # CM2 stepping (newest listed)
39 SubsystemID = 0
40 SubsystemVendorID = 0
41 Status = 0x0000
42 SubClassCode = 0x08
43 ClassCode = 0x80
44 ProgIF = 0x00
45 MaximumLatency = 0x00
46 MinimumGrant = 0xff
47 InterruptLine = 0x20
48 InterruptPin = 0x01
49 BAR0Size = '1kB'
50
51 ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
52 XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
53
54
55 clock = Param.Clock('500MHz', "Clock speed of the device")
56 latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
57 latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
58
59