src/dev/Ethernet.py

   1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.SimObject import SimObject
  30 from m5.params import *
  31 from m5.proxy import *
  32 from Pci import PciDevice, PciConfigData
  33
  34 class EtherInt(SimObject):
  35     type = 'EtherInt'
  36     abstract = True
  37     peer = Param.EtherInt(NULL, "peer interface")
  38
  39 class EtherLink(SimObject):
  40     type = 'EtherLink'
  41     int1 = Param.EtherInt("interface 1")
  42     int2 = Param.EtherInt("interface 2")
  43     delay = Param.Latency('0us', "packet transmit delay")
  44     delay_var = Param.Latency('0ns', "packet transmit delay variability")
  45     speed = Param.NetworkBandwidth('1Gbps', "link speed")
  46     dump = Param.EtherDump(NULL, "dump object")
  47
  48 class EtherBus(SimObject):
  49     type = 'EtherBus'
  50     loopback = Param.Bool(True, "send packet back to the sending interface")
  51     dump = Param.EtherDump(NULL, "dump object")
  52     speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
  53
  54 class EtherTap(EtherInt):
  55     type = 'EtherTap'
  56     bufsz = Param.Int(10000, "tap buffer size")
  57     dump = Param.EtherDump(NULL, "dump object")
  58     port = Param.UInt16(3500, "tap port")
  59
  60 class EtherDump(SimObject):
  61     type = 'EtherDump'
  62     file = Param.String("dump file")
  63     maxlen = Param.Int(96, "max portion of packet data to dump")
  64
  65 class IGbE(PciDevice):
  66     type = 'IGbE'
  67     hardware_address = Param.String("Ethernet Hardware Address")
  68     use_flow_control = Param.Bool(False,
  69         "Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
  70     rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
  71     tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
  72     rx_desc_cache_size = Param.Int(64,
  73         "Number of enteries in the rx descriptor cache")
  74     tx_desc_cache_size = Param.Int(64,
  75         "Number of enteries in the rx descriptor cache")
  76     clock = Param.Clock('500MHz', "Clock speed of the device")
  77
  78 class IGbEPciData(PciConfigData):
  79     VendorID = 0x8086
  80     DeviceID = 0x1075
  81     SubsystemID = 0x1008
  82     SubsystemVendorID = 0x8086
  83     Status = 0x0000
  84     SubClassCode = 0x00
  85     ClassCode = 0x02
  86     ProgIF = 0x00
  87     BAR0 = 0x00000000
  88     BAR1 = 0x00000000
  89     BAR2 = 0x00000000
  90     BAR3 = 0x00000000
  91     BAR4 = 0x00000000
  92     BAR5 = 0x00000000
  93     MaximumLatency = 0x00
  94     MinimumGrant = 0xff
  95     InterruptLine = 0x1e
  96     InterruptPin = 0x01
  97     BAR0Size = '128kB'
  98
  99 class IGbEInt(EtherInt):
 100     type = 'IGbEInt'
 101     device = Param.IGbE("Ethernet device of this interface")
 102
 103
 104
 105 class EtherDevBase(PciDevice):
 106     hardware_address = Param.EthernetAddr(NextEthernetAddr,
 107         "Ethernet Hardware Address")
 108
 109     clock = Param.Clock('0ns', "State machine processor frequency")
 110
 111     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
 112     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
 113     dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
 114     dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
 115
 116     rx_delay = Param.Latency('1us', "Receive Delay")
 117     tx_delay = Param.Latency('1us', "Transmit Delay")
 118     rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
 119     tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
 120
 121     rx_filter = Param.Bool(True, "Enable Receive Filter")
 122     intr_delay = Param.Latency('10us', "Interrupt propagation delay")
 123     rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
 124     tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
 125     rss = Param.Bool(False, "Receive Side Scaling")
 126
 127 class NSGigEPciData(PciConfigData):
 128     VendorID = 0x100B
 129     DeviceID = 0x0022
 130     Status = 0x0290
 131     SubClassCode = 0x00
 132     ClassCode = 0x02
 133     ProgIF = 0x00
 134     BAR0 = 0x00000001
 135     BAR1 = 0x00000000
 136     BAR2 = 0x00000000
 137     BAR3 = 0x00000000
 138     BAR4 = 0x00000000
 139     BAR5 = 0x00000000
 140     MaximumLatency = 0x34
 141     MinimumGrant = 0xb0
 142     InterruptLine = 0x1e
 143     InterruptPin = 0x01
 144     BAR0Size = '256B'
 145     BAR1Size = '4kB'
 146
 147 class NSGigE(EtherDevBase):
 148     type = 'NSGigE'
 149
 150     dma_data_free = Param.Bool(False, "DMA of Data is free")
 151     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
 152     dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 153
 154     configdata = NSGigEPciData()
 155
 156
 157 class NSGigEInt(EtherInt):
 158     type = 'NSGigEInt'
 159     device = Param.NSGigE("Ethernet device of this interface")
 160
 161 class SinicPciData(PciConfigData):
 162     VendorID = 0x1291
 163     DeviceID = 0x1293
 164     Status = 0x0290
 165     SubClassCode = 0x00
 166     ClassCode = 0x02
 167     ProgIF = 0x00
 168     BAR0 = 0x00000000
 169     BAR1 = 0x00000000
 170     BAR2 = 0x00000000
 171     BAR3 = 0x00000000
 172     BAR4 = 0x00000000
 173     BAR5 = 0x00000000
 174     MaximumLatency = 0x34
 175     MinimumGrant = 0xb0
 176     InterruptLine = 0x1e
 177     InterruptPin = 0x01
 178     BAR0Size = '64kB'
 179
 180 class Sinic(EtherDevBase):
 181     type = 'Sinic'
 182
 183     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
 184     tx_max_copy = Param.MemorySize('16kB', "tx max copy")
 185     rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
 186     rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
 187     rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
 188     tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
 189     tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
 190     virtual_count = Param.UInt32(1, "Virtualized SINIC")
 191     zero_copy = Param.Bool(False, "Zero copy receive")
 192     delay_copy = Param.Bool(False, "Delayed copy transmit")
 193     virtual_addr = Param.Bool(False, "Virtual addressing")
 194
 195     configdata = SinicPciData()
 196
 197 class SinicInt(EtherInt):
 198     type = 'SinicInt'
 199     device = Param.Sinic("Ethernet device of this interface")