dev-arm: Implement GICv4.1 GICD_TYPER2 as RES0
[gem5.git] / src / dev / IntPin.py
1 # Copyright 2019 Google, Inc.
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25
26 from m5.params import Port, VectorPort
27
28 INT_SOURCE_ROLE = 'Int Source Pin'
29 INT_SINK_ROLE = 'Int Sink Pin'
30 Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
31
32 # A source pin generally represents a single pin which might connect to
33 # multiple sinks.
34 class IntSourcePin(VectorPort):
35 def __init__(self, desc):
36 super(IntSourcePin, self).__init__(
37 INT_SOURCE_ROLE, desc, is_source=True)
38
39 # Each "physical" pin can be driven by a single source pin since there are no
40 # provisions for resolving competing signals running to the same pin.
41 class IntSinkPin(Port):
42 def __init__(self, desc):
43 super(IntSinkPin, self).__init__(INT_SINK_ROLE, desc)
44
45 # A vector of sink pins represents a bank of physical pins. For instance, an
46 # interrupt controller with many numbered input interrupts could represent them
47 # as a VectorIntSinkPin.
48 class VectorIntSinkPin(VectorPort):
49 def __init__(self, desc):
50 super(VectorIntSinkPin, self).__init__(INT_SINK_ROLE, desc)