src/dev/Pci.py

   1 # Copyright (c) 2005-2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.SimObject import SimObject
  30 from m5.params import *
  31 from m5.proxy import *
  32 from Device import BasicPioDevice, DmaDevice, PioDevice
  33
  34 class PciConfigAll(PioDevice):
  35     type = 'PciConfigAll'
  36     cxx_header = "dev/pciconfigall.hh"
  37     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  38     pio_latency = Param.Latency('30ns', "Programmed IO latency")
  39     bus = Param.UInt8(0x00, "PCI bus to act as config space for")
  40     size = Param.MemorySize32('16MB', "Size of config space")
  41
  42
  43 class PciDevice(DmaDevice):
  44     type = 'PciDevice'
  45     cxx_class = 'PciDev'
  46     cxx_header = "dev/pcidev.hh"
  47     abstract = True
  48     platform = Param.Platform(Parent.any, "Platform this device is part of.")
  49     config = SlavePort("PCI configuration space port")
  50     pci_bus = Param.Int("PCI bus")
  51     pci_dev = Param.Int("PCI device number")
  52     pci_func = Param.Int("PCI function code")
  53     pio_latency = Param.Latency('30ns', "Programmed IO latency")
  54     config_latency = Param.Latency('20ns', "Config read or write latency")
  55
  56     VendorID = Param.UInt16("Vendor ID")
  57     DeviceID = Param.UInt16("Device ID")
  58     Command = Param.UInt16(0, "Command")
  59     Status = Param.UInt16(0, "Status")
  60     Revision = Param.UInt8(0, "Device")
  61     ProgIF = Param.UInt8(0, "Programming Interface")
  62     SubClassCode = Param.UInt8(0, "Sub-Class Code")
  63     ClassCode = Param.UInt8(0, "Class Code")
  64     CacheLineSize = Param.UInt8(0, "System Cacheline Size")
  65     LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
  66     HeaderType = Param.UInt8(0, "PCI Header Type")
  67     BIST = Param.UInt8(0, "Built In Self Test")
  68
  69     BAR0 = Param.UInt32(0x00, "Base Address Register 0")
  70     BAR1 = Param.UInt32(0x00, "Base Address Register 1")
  71     BAR2 = Param.UInt32(0x00, "Base Address Register 2")
  72     BAR3 = Param.UInt32(0x00, "Base Address Register 3")
  73     BAR4 = Param.UInt32(0x00, "Base Address Register 4")
  74     BAR5 = Param.UInt32(0x00, "Base Address Register 5")
  75     BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
  76     BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
  77     BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
  78     BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
  79     BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
  80     BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
  81     BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO")
  82     BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO")
  83     BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO")
  84     BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
  85     BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
  86     BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
  87
  88     CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
  89     SubsystemID = Param.UInt16(0x00, "Subsystem ID")
  90     SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
  91     ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
  92     InterruptLine = Param.UInt8(0x00, "Interrupt Line")
  93     InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
  94     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
  95     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
  96
  97